[all-commits] [llvm/llvm-project] 3516ad: [RISCV] Update SpacemiT X60 scheduling latencies b...

[Mikhail R. Gadelha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3516ad05dfd674d731487cb67bbfe48f7e1fda9c
      https://github.com/llvm/llvm-project/commit/3516ad05dfd674d731487cb67bbfe48f7e1fda9c
  Author: Mikhail R. Gadelha <mikhail at igalia.com>
  Date:   2025-06-19 (Thu, 19 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s

  Log Message:
  -----------
  [RISCV] Update SpacemiT X60 scheduling latencies based on hardware measurements (#144730)

This patch updates the RISC-V SpacemiT X60 scheduling model with latency
values collected from the X60 hardware. The previous values were
empirically derived but were slightly off.

  Changes:
  - LoadLatency (baseline for load instructions): 5 --> 3 cycles
  - Memory operations: unified at 4 cycles
  - Atomic loads/stores: 5 --> 8 cycles
  - Atomic RMW operations: 5 --> 12 cycles

Hardware-measured values provide more accurate instruction scheduling
for the in-order X60 core. Testing shows NFC across benchmarks except
for 523.xalancbmk_r (known to be noisy).

https://lnt.lukelau.me/db_default/v4/nts/663?compare_to=657



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