[all-commits] [llvm/llvm-project] 408e55: [RISCV] Add support for handling one tied operand ...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
      https://github.com/llvm/llvm-project/commit/408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
  Author: quic_hchandel <quic_hchandel at quicinc.com>
  Date:   2025-06-19 (Thu, 19 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/MC/RISCV/xqciac-valid.s
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV] Add support for handling one tied operand in the source instruction for compress patterns (#143660)

This update enables compress patterns to handle one tied operand in
source instructions, which was previously unsupported. Qualcomm's uC
extension Xqci includes several instructions with tied operands that can
be compressed into smaller forms. This change adds the necessary support
to enable such compression. Additionally, a compress pattern for the
qc.muliadd instruction has been implemented.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications