[all-commits] [llvm/llvm-project] 590066: [NVPTX] Add family-specific architectures support ...

[Rajat Bajpai via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 590066bee70db37636311881c5b232464d6d4aec
      https://github.com/llvm/llvm-project/commit/590066bee70db37636311881c5b232464d6d4aec
  Author: Rajat Bajpai <rbajpai at nvidia.com>
  Date:   2025-06-19 (Thu, 19 Jun 2025)

  Changed paths:
    M llvm/docs/NVPTXUsage.rst
    M llvm/lib/Target/NVPTX/NVPTX.td
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
    M llvm/test/CodeGen/NVPTX/sm-version.ll

  Log Message:
  -----------
  [NVPTX] Add family-specific architectures support (#141899)

This change adds family-specific architecture variants support added in [PTX ISA
8.8](https://docs.nvidia.com/cuda/parallel-thread-execution/#ptx-isa-version-8-8).
These architecture variants have "f" suffix. For example, sm_100f.

This change doesn't promote existing features to family-specific
architecture.



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