[all-commits] [llvm/llvm-project] 6e5ee4: [RISCV] Save vector registers in interrupt handler...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
      https://github.com/llvm/llvm-project/commit/6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-18 (Wed, 18 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCallingConv.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll

  Log Message:
  -----------
  [RISCV] Save vector registers in interrupt handler. (#143808)

Corresponding gcc bug report
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110665

The generated code is pretty awful.



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