[all-commits] [llvm/llvm-project] 835d30: [AArch64] improve zero-cycle regmov test (#143680)

[Tomer Shafir via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 835d3034fe96931cf907537b51b9cdd87b59d3ad
      https://github.com/llvm/llvm-project/commit/835d3034fe96931cf907537b51b9cdd87b59d3ad
  Author: Tomer Shafir <tomer.shafir8 at gmail.com>
  Date:   2025-06-18 (Wed, 18 Jun 2025)

  Changed paths:
    A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
    R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll

  Log Message:
  -----------
  [AArch64] improve zero-cycle regmov test (#143680)

- Add a `gpr32` suffix to test name to denote the specific register
class being checked
- Expand `-mtriple=arm64-apple-ios` to `-march=arm64` to broaden the
test context to the generic architecture, as the specific triple is not
required
- Port `bl` match to Linux too via the regex: `{{_?foo}}`
- Advance `-mcpu=cyclone` to the newer M series major `-mcpu=apple-m1`
- Use `-mcpu` so that `-mattr=-zcm` has a real effect
- Add a test that generic arm64 doesn't optimize for ZCM
- Distinguish 4 different assembly layouts: NOTCPU, CPU, NOTATTR, ATTR
- Fix broken test logic, for example: `; NOT: mov [[REG2:w[0-9]+]], w3`
matched `mov w1, w3` then `REG2` captured `w1` but then `; NOT: mov w1,
[[REG2]]` matched by prefix `mov, w1, w19` even though it should have
matched `mov w1, w1`. This change adds explicit matches for all of the
generated copies.



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