[all-commits] [llvm/llvm-project] b53c1e: [AArch64] Add ISel for postindex ld1/st1 in big-en...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
      https://github.com/llvm/llvm-project/commit/b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
  Author: John Brawn <john.brawn at arm.com>
  Date:   2025-06-18 (Wed, 18 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll

  Log Message:
  -----------
  [AArch64] Add ISel for postindex ld1/st1 in big-endian (#144387)

When big-endian we need to use ld1/st1 for vector loads and stores so
that we get the elements in the correct order, but this prevents
postindex addressing from being used. Fix this by adding the appropriate
ISel patterns, plus the relevant changes in ISelLowering and
ISelDAGToDAG to cause postindex addressing to be used.



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