[all-commits] [llvm/llvm-project] a02afb: AVR: Migrate to the new relocation specifier repre...
Mel Chen via All-commits
all-commits at lists.llvm.org
Wed Jun 18 01:11:23 PDT 2025
Branch: refs/heads/users/wangpc-pp/spr/main.riscv-support-non-power-of-2-types-when-expanding-memcmp
Home: https://github.com/llvm/llvm-project
Commit: a02afb0def589ec28f8240ff15760e5f241b833c
https://github.com/llvm/llvm-project/commit/a02afb0def589ec28f8240ff15760e5f241b833c
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
Log Message:
-----------
AVR: Migrate to the new relocation specifier representation
Define printImpl and evaluateAsRelocationImpl within AVRMCAsmInfo.
Commit: 199428e0472c80d9b742d0a3e492ab902005fb6a
https://github.com/llvm/llvm-project/commit/199428e0472c80d9b742d0a3e492ab902005fb6a
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
Log Message:
-----------
[bazel][lld] Remove unneeded dependencies. (#144455)
As far as I can tell these are not used in any includes in their
respective targets, and building all of LLD with
```
bazel build --config=generic_clang @llvm-project//lld/...
```
still works.
Commit: 30350afd023c4e9583d5a8bbfd56af7c354923fa
https://github.com/llvm/llvm-project/commit/30350afd023c4e9583d5a8bbfd56af7c354923fa
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
Log Message:
-----------
MCSpecifierExpr: Remove unused virtual functions
... now that all targets using MCSpecifierExpr have migrated to
XXXMCAsmInfo::printExpr/evaluateAsRelocatableImpl.
Commit: 7caeec599998bd8aa01d498574e148e4e9c982db
https://github.com/llvm/llvm-project/commit/7caeec599998bd8aa01d498574e148e4e9c982db
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[NFC][flang][OpenMP] Unify `genSectionsOp`'s prototype to match other `genXXXOp` functions (#144013)
Unifies the prototype of `genSectionsOp` to match other ops generators.
Doing so, we are able to call `genSectionsOp` directtly from
`genOMPDispatch` instead of the special handling needed now to pass the
section blocks. This is useful because now we can handle symbol mapping
scopes easier for nested OpenMP directives. See
https://github.com/llvm/llvm-project/pull/143706#issuecomment-2965344723
and the following discussion for more info.
Commit: b5dbf8210a57b986b9802304745f4c5c108cf37b
https://github.com/llvm/llvm-project/commit/b5dbf8210a57b986b9802304745f4c5c108cf37b
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/do_concurrent_delayed_locality.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
M flang/test/Lower/do_concurrent_local_default_init.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops3.f90
Log Message:
-----------
[flang] Enable delayed localization by default for `do concurrent` (#144074)
Reintroduces changes from
https://github.com/llvm/llvm-project/issues/143897. A fix for the
reported problem in https://github.com/llvm/llvm-project/issues/143897
is hopefully resolved in
https://github.com/llvm/llvm-project/pull/144027.
This PR aims to make it easier and more self-contained to revert the
switch/flag if we discover any problems with enabling it by default.
Commit: 2dc58e02cbce83784a38b4cc33f83529ad1a7c7e
https://github.com/llvm/llvm-project/commit/2dc58e02cbce83784a38b4cc33f83529ad1a7c7e
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/target-parallel-private.f90
R flang/test/Lower/OpenMP/Todo/target-teams-private.f90
A flang/test/Lower/OpenMP/target-parallel-private.f90
A flang/test/Lower/OpenMP/target-teams-private.f90
Log Message:
-----------
[flang][OpenMP] Add symbol table scopes for `teams` and `parallel` (#144015)
Adds symbol map scopes for standalone `teams` and `parallel` constructs.
This is required to properly bind the privatized symbols in both
constructs so that nested constructs can find them.
Resolves https://github.com/llvm/llvm-project/issues/116428.
Commit: 84d879d6999b61cea3f9f200df57653f5a51ee41
https://github.com/llvm/llvm-project/commit/84d879d6999b61cea3f9f200df57653f5a51ee41
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Log Message:
-----------
[RISCV] Rename Relocation QC_E_JUMP_PLT to QC_E_CALL_PLT (#143998)
The semantics and definition of this relocation are unchanged. The new
name reflects that instructions with the relocation should be assumed to
clobber non-callee-saved registers, as with the R_RISCV_CALL_PLT
relocation.
The name was changed in v0.2 of the ABI extensions:
https://github.com/quic/riscv-elf-psabi-quic-extensions/releases/tag/v0.2
Commit: c0ac95181eededc85027d63fe9f97bc742b7a552
https://github.com/llvm/llvm-project/commit/c0ac95181eededc85027d63fe9f97bc742b7a552
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Update Xqci to v0.13.0 (#144398)
Commit: 98c6c371d6dc09454d541474ef65a0e47c4baae6
https://github.com/llvm/llvm-project/commit/98c6c371d6dc09454d541474ef65a0e47c4baae6
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Xqccmp v0.3 (#137854)
All the changes for v0.2 and v0.3 are either already implemented, or
irrelevant to the compiler implementation.
Commit: e86740e6003739a41139d94e1643a3207f8fd8f8
https://github.com/llvm/llvm-project/commit/e86740e6003739a41139d94e1643a3207f8fd8f8
Author: no92 <no92 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
A clang/lib/Driver/ToolChains/Managarm.cpp
A clang/lib/Driver/ToolChains/Managarm.h
M clang/lib/Lex/InitHeaderSearch.cpp
A clang/test/Driver/Inputs/basic_managarm_tree/lib/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/aarch64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/v1/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/riscv64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/x86_64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib64/.keep
A clang/test/Driver/managarm.cpp
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-macros-no-warnings.c
Log Message:
-----------
[clang] Add managarm support (#139271)
This PR is part of a series to upstream managarm support, as laid out in
the
[RFC](https://discourse.llvm.org/t/rfc-new-proposed-managarm-support-for-llvm-and-clang-87845/85884/1).
This PR is a follow-up to #87845 and #138854.
Commit: 41b9d28327bf20befe63a683b2a2f90670837b2f
https://github.com/llvm/llvm-project/commit/41b9d28327bf20befe63a683b2a2f90670837b2f
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M bolt/test/lit.local.cfg
Log Message:
-----------
[BOLT][NFC] Using target_triple in lit config (#144078)
Commit: 7e6c1bd3edf4fc19be70587a4ac33a76bab78c02
https://github.com/llvm/llvm-project/commit/7e6c1bd3edf4fc19be70587a4ac33a76bab78c02
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT][NFCI] Simplify DataAggregator using traces (#143289)
Consistently apply traces as defined in #127125 for branch profile
aggregation. This combines branches and fall-through records into one.
With large input binaries/profiles, the speed up in aggregation time
(`-time-aggr`, wall time):
- perf.data, pre-BOLT input: 154.5528s -> 144.0767s
- pre-aggregated data, pre-BOLT input: 15.1026s -> 9.0711s
- pre-aggregated data, BOLTed input: 15.4871s -> 10.0077s
Test Plan: NFC
Commit: 80b79ce432bbe12701fd9fe495ff9feeb5e4b9ca
https://github.com/llvm/llvm-project/commit/80b79ce432bbe12701fd9fe495ff9feeb5e4b9ca
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/ConstProp/loads.ll
Log Message:
-----------
[ConstantFolding] Handle reading from type padding (#144330)
ReadDataFromGlobal() did not handle reads from the padding of types (in
the sense of type store size != type alloc size, rather than struct
padding).
Return zero in that case.
Fixes https://github.com/llvm/llvm-project/issues/144279.
Commit: bb70023cbfecf7880e4cc89966947ef475e070e9
https://github.com/llvm/llvm-project/commit/bb70023cbfecf7880e4cc89966947ef475e070e9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/test/Transforms/DeadStoreElimination/trivial-dse-calls.ll
Log Message:
-----------
[MemoryLocation][DSE] Allow other read effects in MemoryLocation::getForDest() (#144343)
MemoryLocation::getForDest() returns a (potentially) written location,
while still allowing other reads. Currently, this is limited to
argmemonly functions. However, we can ignore other (non-argmem) read
effects here for the same reason we can ignore argument reads.
Fixes https://github.com/llvm/llvm-project/issues/144300.
Proof: https://alive2.llvm.org/ce/z/LKq_dc
Commit: 632151fbeea972f4aa3c14921eca1e45c07646f3
https://github.com/llvm/llvm-project/commit/632151fbeea972f4aa3c14921eca1e45c07646f3
Author: gaynor-anthropic <gaynor at anthropic.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/add.ll
Log Message:
-----------
InstCombine: improve optimizations for ceiling division with no overflow (#142869)
Fixes #142497.
Alive2: https://alive2.llvm.org/ce/z/CeaHaH
The contents of this pull request were substantially written using
claude-code. I've reviewed to the best of my ability (it's been years
since I did any compilers work).
---------
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: c564ebba22ae9af315e08789c628810a3bbcf3df
https://github.com/llvm/llvm-project/commit/c564ebba22ae9af315e08789c628810a3bbcf3df
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineEXTRACT_SUBVECTOR - move AVX1 ANDNP comment and fold back together. NFC.
These appear to have been split by a merge at some point.
Commit: cb355def9561e2d1d4b363f44dcedf5522f0f8a1
https://github.com/llvm/llvm-project/commit/cb355def9561e2d1d4b363f44dcedf5522f0f8a1
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Lower/OpenMP/Todo/omp-clause-indirect.f90
A flang/test/Parser/OpenMP/declare-target-indirect-tree.f90
A flang/test/Semantics/indirect01.f90
A flang/test/Semantics/indirect02.f90
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[Flang][OpenMP] Add Parsing support for Indirect Clause (#143505)
As part of OpenMP Version 5.1, support for the `indirect` clause was
added for the `declare target` directive. This clause should follow an
`enter` clause, and allows procedure calls to be done indirectly through
OpenMP.
This adds Parsing support for the clause, along with semantics checks.
Currently, lowering for the clause is not supported so a TODO message
will be outputted to the user. It also performs version checking as
`indirect` is only support in OpenMP 5.1 or greater.
See also: #110008
Commit: 90905a638e483dd9040c153785148fcea7c3e412
https://github.com/llvm/llvm-project/commit/90905a638e483dd9040c153785148fcea7c3e412
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp
A lldb/test/Shell/ObjectFile/XCOFF/symbol-info.yaml
A lldb/test/Shell/ObjectFile/XCOFF/symbol-info32.yaml
Log Message:
-----------
[lldb][AIX] Added XCOFF ParseSymtab handling (#141577)
This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:
1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601
**Description:**
Adding ParseSymtab logic after creating sections. It is able to handle
both 32 and 64 bit symbols,
without the need to add template logic.
This is an incremental PR on top of my previous couple of XCOFF support
commits.
Commit: 437945b28838c71fb32a76f6433cef8807967f71
https://github.com/llvm/llvm-project/commit/437945b28838c71fb32a76f6433cef8807967f71
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Log Message:
-----------
[AArch64][SVE] Move incorrectly placed assert (#144318)
This assert is only valid if FPAfterSVECalleeSaves is true, for the
default layout resolving CSR works correctly.
Commit: 85b110e0419af4b1b9a238b6978029e20010e794
https://github.com/llvm/llvm-project/commit/85b110e0419af4b1b9a238b6978029e20010e794
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/docs/Dialects/Vector.md
Log Message:
-----------
[mlir][vector] Add documentation note on adding new ops (#144308)
This adds a note requesting that additions of new ops to the Vector
dialect go through an RFC process. The goal is to clarify expectations
for contributors.
Note: this documents an existing (though previously unwritten)
convention. See, e.g.:
* https://discourse.llvm.org/t/rfc-adding-vector-to-elements-op-to-the-vector-dialect
* https://discourse.llvm.org/t/rfc-improving-gather-codegen-for-vector-dialect
Commit: e2551c14d0d9180ccaef9d33c524d83e7813a361
https://github.com/llvm/llvm-project/commit/e2551c14d0d9180ccaef9d33c524d83e7813a361
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/test/Analysis/NewDelete-checker-test.cpp
Log Message:
-----------
[analyzer] Fix a false memory leak reports involving placement new (#144341)
Placement new does not allocate memory, so it should not be reported as
a memory leak. A recent MallocChecker refactor changed inlining of
placement-new calls with manual evaluation by MallocChecker.
https://github.com/llvm/llvm-project/commit/339282d49f5310a2837da45c0ccc19da15675554
This change avoids marking the value returned by placement new as
allocated and hence avoids the false leak reports.
Note that the there are two syntaxes to invoke placement new:
`new (p) int` and an explicit operator call `operator new(sizeof(int), p)`.
The first syntax was already properly handled by the engine.
This change corrects handling of the second syntax.
CPP-6375
Commit: 308b97a5d48583680f56b888165295c62744b9e5
https://github.com/llvm/llvm-project/commit/308b97a5d48583680f56b888165295c62744b9e5
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/Transforms/LICM/funclet.ll
Log Message:
-----------
[LICM] Regenerate test checks (NFC)
Commit: 2c90ebf3a79e25db3e6bcd9b3a66590b5996de4d
https://github.com/llvm/llvm-project/commit/2c90ebf3a79e25db3e6bcd9b3a66590b5996de4d
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
A mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir
Log Message:
-----------
[OMPIRBuilder][debug] Don't drop debug info for loop constructs. (#144393)
In OMPIRBuilder, we have many cases where we don't handle the debug
location correctly while changing the location or insertion point. This
is one of those cases.
Please see the following test program.
```
program main
implicit none
integer i, j
integer array(16384)
!$omp target teams distribute
DO i=1,16384
!$omp parallel do
DO j=1,16384
array(j) = i
ENDDO
!$omp end parallel do
ENDDO
!$omp end target teams distribute
print *, array
end program main
```
When tried to compile with the follownig command
`flang -g -O2 -fopenmp test.f90 -o test --offload-arch=gfx90a`
will fail in the verification with the following errors: `!dbg
attachment points at wrong subprogram for function`
This happens because we were dropping the debug location in the
createCanonicalLoop and the call to the functions like
`__kmpc_distribute_static_4u` get generated without a debug location.
When it gets inlined, the locations inside it are not adjusted as the
call instruction does not have the debug locations
(`llvm/lib/Transforms/Utils/InlineFunction.cpp:fixupLineNumbers`). Later
Verifier finds that the caller have instructions with debug locations
that point to another function and fails.
The fix is simple to not drop the debug location.
Commit: 0f8c72160ec001599ecb29f0fa182c5550f5dd0a
https://github.com/llvm/llvm-project/commit/0f8c72160ec001599ecb29f0fa182c5550f5dd0a
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/preferred_name_header_unit.cpp
Log Message:
-----------
[C++20][Modules] Disable preferred_name when writing a C++20 header unit (#144377)
https://reviews.llvm.org/D130331 added workaround for named modules
only. But the same issue happens for headees units. Link issue #56490
Commit: 26d082d330e4d8d1fc3194b4b87ede9332a297f5
https://github.com/llvm/llvm-project/commit/26d082d330e4d8d1fc3194b4b87ede9332a297f5
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.cpp
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-value-param.rst
A clang-tools-extra/test/clang-tidy/checkers/performance/unnecessary-value-param-coroutine.cpp
Log Message:
-----------
[clang-tidy][performance-unnecessary-value-param] Avoid in coroutines (#140912)
Summary:
Replacing by-value parameters with passing by-reference is not safe for
coroutines because the caller may be executed in parallel with the
callee, which increases the chances of resulting in dangling references
and hard-to-find crashes. See for the reference
[cppcoreguidelines-avoid-reference-coroutine-parameters](https://clang.llvm.org/extra/clang-tidy/checks/cppcoreguidelines/avoid-reference-coroutine-parameters.html).
Test Plan: check-clang-tools
Commit: 5dc632dd56c61fb768424cc8027760490683d00d
https://github.com/llvm/llvm-project/commit/5dc632dd56c61fb768424cc8027760490683d00d
Author: Rolf Morel <rolf.morel at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/utils/vscode/package-lock.json
M mlir/utils/vscode/package.json
Log Message:
-----------
[MLIR][VSCode] update packages to fix CVE-2022-25883 and CVE-2022-3517 (#144479)
Fixes issue #140869.
Commit: 64bd4858dc2d64311622e793b66094b07ca7bdc5
https://github.com/llvm/llvm-project/commit/64bd4858dc2d64311622e793b66094b07ca7bdc5
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
Log Message:
-----------
Amend enviroment variables in bazel - change from #144391 (#144484)
Commit: e5ad7f4556ba4f31380153f70a8c6186926764e2
https://github.com/llvm/llvm-project/commit/e5ad7f4556ba4f31380153f70a8c6186926764e2
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
Log Message:
-----------
[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)
The `RISCVIndirectBranchTracking` pass inserts `lpad` instruction and
could change the basic block alignment, so this should not happen after
the branch relaxation as the adjusted offset is possible to exceed the
branch range.
Commit: 97e17e15957bf6f03923ca46301b32cad507f34b
https://github.com/llvm/llvm-project/commit/97e17e15957bf6f03923ca46301b32cad507f34b
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/do_concurrent_delayed_locality.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
M flang/test/Lower/do_concurrent_local_default_init.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops3.f90
Log Message:
-----------
Revert "[flang] Enable delayed localization by default for `do concurrent` (#144074)" (#144476)
This reverts commit b5dbf8210a57b986b9802304745f4c5c108cf37b.
Reverting again due to gfortran failure:
https://lab.llvm.org/buildbot/#/builders/17/builds/8868
Commit: dfd00edbabef8094bec663cca9314a950ec56e0d
https://github.com/llvm/llvm-project/commit/dfd00edbabef8094bec663cca9314a950ec56e0d
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
Fix for #144391 not fully addressed by #144484 (#144488)
Commit: 277b2b6da70b488e08b0f0eecba2a4cd1dd01129
https://github.com/llvm/llvm-project/commit/277b2b6da70b488e08b0f0eecba2a4cd1dd01129
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineCastedMaskArithmetic - convert to SDPatternMatch matching. NFC. (#144472)
Commit: aa01e8e9cff9e754b47be57b2f85b962cf1ec9fb
https://github.com/llvm/llvm-project/commit/aa01e8e9cff9e754b47be57b2f85b962cf1ec9fb
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-task-charbox.mlir
Log Message:
-----------
[mlir][OpenMP] Fix broken insertion point for charbox with omp task (#143112)
Fixes #142365
Commit: 00709c306d0a0f60d169ab25f612ed6715e16743
https://github.com/llvm/llvm-project/commit/00709c306d0a0f60d169ab25f612ed6715e16743
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
AArch64: Fix hardcoding calling convention of sincos_stret (NFC) (#144336)
Commit: 4c8f43440955c93a54b9547421513867bc81788a
https://github.com/llvm/llvm-project/commit/4c8f43440955c93a54b9547421513867bc81788a
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bugfix-124477.m
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[analyzer] Conversion to CheckerFamily: NullabilityChecker (#143735)
This commit converts NullabilityChecker to the new checker family
framework that was introduced in the recent commit
6833076a5d9f5719539a24e900037da5a3979289
This commit removes the dummy checker `nullability.NullabilityBase`
because it was hidden from the users and didn't have any useful role
except for helping the registration of the checker parts in the old
ad-hoc system (which is replaced by the new standardized framework).
Except for the removal of this dummy checker, no functional changes
intended.
Commit: 6f2983765983b9403ae40430da8034d2d1b6e8a4
https://github.com/llvm/llvm-project/commit/6f2983765983b9403ae40430da8034d2d1b6e8a4
Author: Ying Yi <ying.yi at sony.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/ignored-pch.cpp
A clang/test/PCH/Inputs/ignored-pch.h
A clang/test/PCH/ignored-pch.c
Log Message:
-----------
Reland: "[Frontend][PCH]-Add support for ignoring PCH options (-ignore-pch). (#142409)" (#143614)
Visual Studio has an argument to ignore all PCH related switches.
clang-cl has also support option /Y-. Having the same option in clang
would be helpful. This commit is to add support for ignoring PCH options
(-ignore-pch).
The commit includes:
1. Implement -ignore-pch as a Driver option.
2. Add a Driver test and a PCH test.
3. Add a section of -ignore-pch to user manual.
4. Add a release note for the new option '-ignore-pch'.
The change since the original landing:
1. preprocessing-only mode doesn't imply that -include-pch is disabled.
Co-authored-by: Matheus Izvekov <mizvekov at gmail.com>
Commit: 7eda8274fed9a87f25a54616f5009bb68e511b77
https://github.com/llvm/llvm-project/commit/7eda8274fed9a87f25a54616f5009bb68e511b77
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir
Log Message:
-----------
[MLIR] Integration tests for lowering vector.contract to SVE FEAT_I8MM (#140573)
Commit: c377ce1216a8ce73c940d2366a7bf223790f43b4
https://github.com/llvm/llvm-project/commit/c377ce1216a8ce73c940d2366a7bf223790f43b4
Author: Mary Kassayova <mary.kassayova at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fveclib.c
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
A llvm/test/CodeGen/AArch64/replace-with-veclib-libmvec-scalable.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-libmvec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[AArch64][VecLib] Add libmvec support for AArch64 targets (#143696)
This patch adds support for the `libmvec` vector library on AArch64
targets. Currently, all `libmvec` functions in GLIBC version 2.40 are
supported. The full list of math functions enabled can be found
[here](https://github.com/bminor/glibc/blob/96abd59bf2a11ddd4e7ccaac840ec13c0b62d3ba/sysdeps/aarch64/fpu/Versions)
(up to GLIBC 2.40).
Previously, `libmvec` was only supported on x86_64 targets. Attempts to
use it on AArch64 resulted in the following error from Clang:
`unsupported option 'libmvec' for target 'aarch64'`.
Commit: 465e3ce9f10019db071dc7794ae9ab22f9fc76f7
https://github.com/llvm/llvm-project/commit/465e3ce9f10019db071dc7794ae9ab22f9fc76f7
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-sdiv-pow2.ll
Log Message:
-----------
[LLVM][CodeGen] Lower ConstantInt vectors like shufflevector base splats. (#144395)
ConstantInt vectors utilise DAG.getConstant() when constructing the
initial DAG. This can have the effect of legalising the constant before
the DAG combiner is run, significant altering the generated code. To
mitigate this (hopefully as a temporary measure) we instead try to
construct the DAG in the same way as shufflevector based splats.
Commit: 71f72f4d5d1b820a3e6147289547821332eaf115
https://github.com/llvm/llvm-project/commit/71f72f4d5d1b820a3e6147289547821332eaf115
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] Move foldMaskedMerge before visitAND. NFC.
Reduces diff in #144342
Commit: d3f13a0732c2d937a4c12cb8b1a61992ee5b0d9c
https://github.com/llvm/llvm-project/commit/d3f13a0732c2d937a4c12cb8b1a61992ee5b0d9c
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] MemorySSA for GVN: embed the memory state in symbolic expressions (#123218)
While migrating towards MemorySSA, account for the memory state modeled
by MemorySSA by hashing it, when computing the symbolic expressions for
the memory operations. Likewise, when phi-translating while walking the
CFG for PRE possibilities, see if the value number of an operand may be
refined with one of the value from the incoming edges of the MemoryPhi
associated to the current phi.
Co-authored-by: Momchil Velikov <momchil.velikov at arm.com>
Commit: ce96fdde54c379fa3893f3f07d8233df9e16b9e2
https://github.com/llvm/llvm-project/commit/ce96fdde54c379fa3893f3f07d8233df9e16b9e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpStack.cpp
Log Message:
-----------
[clang][bytecode] Keep the last chunk in InterpStack::clear() (#144487)
We call clear when checking for potential constant expressions, but that
used to free all the chunks. Keep the last one so we don't have to
re-allocate it.
Commit: 576ced56d78b48e658b0a170603388e4802f6311
https://github.com/llvm/llvm-project/commit/576ced56d78b48e658b0a170603388e4802f6311
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBlock.cpp
Log Message:
-----------
[clang][bytecode] Simplify Block::replacePointer() (#144490)
Try to do less work here instead of a full remove + add.
Commit: 49c6235d1fb3bcecfe37a8e41bec69d6c7dc86ff
https://github.com/llvm/llvm-project/commit/49c6235d1fb3bcecfe37a8e41bec69d6c7dc86ff
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
Log Message:
-----------
[PowerPC] Regenerate MIR test checks (NFC)
Commit: 2d336e7c5e821383816a9dca080f713747cc9e1e
https://github.com/llvm/llvm-project/commit/2d336e7c5e821383816a9dca080f713747cc9e1e
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/DivZeroChecker.cpp
M clang/test/Analysis/taint-generic.c
Log Message:
-----------
[analyzer] Avoid contradicting assumption in tainted div-by-0 error node (#144491)
This patch corrects the state of the error node generated by the
core.DivideZero checker when it detects potential division by zero
involving a tainted denominator.
The checker split in
https://github.com/llvm/llvm-project/pull/106389/commits/91ac5ed10a154410c246d985752c1bbfcf23b105
started to introduce a conflicting assumption about the denominator into
the error node:
Node with the Bug Report "Division by a tainted value, possibly zero"
has an assumption "denominator != 0".
This has been done as a shortcut to continue analysis with the correct
assumption *after* the division - if we proceed, we can only assume the
denominator was not zero. However, this assumption is introduced
one-node too soon, leading to a self-contradictory error node.
In this patch, I make the error node with assumption of zero denominator
fatal, but allow analysis to continue on the second half of the state
split with the assumption of non-zero denominator.
---
CPP-6376
Commit: 990d2540bf0545cc4024c3718069f6d0b42c461b
https://github.com/llvm/llvm-project/commit/990d2540bf0545cc4024c3718069f6d0b42c461b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] isAddSubOrSubAdd - convert to SDPatternMatch matching. NFC. (#144486)
Commit: 875b36a8742437b95f623bab1e0332562c7b4b3f
https://github.com/llvm/llvm-project/commit/875b36a8742437b95f623bab1e0332562c7b4b3f
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
Log Message:
-----------
[mlir] fix MemRefToLLVM lowering of atomic operations (#139045)
We have been confusingly, and arguably incorrectly, lowering `m**imumf`
atomic RMW operations in the MemRef dialect to `fm**` atomic RMW
operations in the LLVM dialect, which have different NaN-propagation
semantics: `m**imumf` propagates NaNs from either operand whereas
`fm**`, which lowers to the `fm**num` intrinsic returns the non-NaN
operand. This also contradicts the lowering of `arith.m**imumf` and
`arith.m**numf` operations.
Change the lowering to match the terminology in arith.
Add tests for these lowerings.
Keep a debug message in case of surprising behavior downstream (the code
may be producing more NaNs now).
Commit: 9700930bd90a099f702332cf86dd898f00840f99
https://github.com/llvm/llvm-project/commit/9700930bd90a099f702332cf86dd898f00840f99
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] detectZextAbsDiff - convert to SDPatternMatch matching. NFC. (#144498)
Match the entire ABS(SUB(ZEXT(vXi8),ZEXT(vXi8))) pattern and simplify the logic in combineBasicSADPattern accordingly
Commit: 12611a7fc71376e88aa01e3f0bbc74517f1a1703
https://github.com/llvm/llvm-project/commit/12611a7fc71376e88aa01e3f0bbc74517f1a1703
Author: Denzel-Brian Budii <73462654+chios202 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Query/Matcher/MatchFinder.h
M mlir/include/mlir/Query/Matcher/MatchersInternal.h
M mlir/include/mlir/Query/Matcher/SliceMatchers.h
M mlir/include/mlir/Query/Matcher/VariantValue.h
M mlir/lib/Query/Matcher/CMakeLists.txt
A mlir/lib/Query/Matcher/MatchersInternal.cpp
M mlir/lib/Query/Matcher/RegistryManager.cpp
M mlir/lib/Query/Matcher/VariantValue.cpp
M mlir/lib/Query/Query.cpp
A mlir/test/mlir-query/backward-slice-union.mlir
R mlir/test/mlir-query/complex-test.mlir
A mlir/test/mlir-query/forward-slice-by-predicate.mlir
A mlir/test/mlir-query/logical-operator-test.mlir
A mlir/test/mlir-query/slice-function-extraction.mlir
M mlir/tools/mlir-query/mlir-query.cpp
Log Message:
-----------
[mlir] Improve mlir-query by adding matcher combinators (#141423)
Whereas backward-slice matching provides support to limit traversal by
specifying the desired depth level, this pull request introduces support
for limiting traversal with a nested matcher (adding forward-slice
also). It also adds support for variadic operators, including `anyOf`
and `allOf`. Rather than simply stopping traversal when an operation
named foo is encountered, one can now define a matcher that specifies
different exit conditions. Variadic support implementation within
mlir-query is very similar to clang-query.
Commit: 087d83e0c6d94c1ad6a68b089950d05185d0e043
https://github.com/llvm/llvm-project/commit/087d83e0c6d94c1ad6a68b089950d05185d0e043
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] vectorizeStores: Name things a bit more clearly (NFC) (#144511)
I believe the new variable names better convey their purpose. However, I
also believe that function is more complex than it needs to be, and this
tiny patch should be seen as a first step towards (maybe) further
refactoring.
The previous names were very generic (Size, Sz, Cnt, StartIdx). This
made it easy to get confused given that the vecotrizeStores() function
is already complex enough.
My hope would be to eventually have a function concise enough to clearly
see what are the different strategies being attempted to vectorise a
group of related store instructions.
Commit: cb011d3199e1160ad2706cb5b1d43692fa4784d8
https://github.com/llvm/llvm-project/commit/cb011d3199e1160ad2706cb5b1d43692fa4784d8
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/cuda_wrappers/bits/c++config.h
Log Message:
-----------
[CUDA][HIP] Add a __device__ version of std::__glibcxx_assert_fail() (#136133)
libstdc++ 15 uses the non-constexpr function
std::__glibcxx_assert_fail() to trigger compilation errors when the
__glibcxx_assert(cond) macro is used in a constantly evaluated context.
Compilation fails when using code from the libstdc++ (such as
std::array) on device code, since these assertions invoke a
non-constexpr host function from device code.
This patch proposes a cuda wrapper header "bits/c++config.h" which adds
a __device__ version of std::__glibcxx_assert_fail().
Solves SWDEV-518041
Commit: 3377b56338d93760507e1707ebde48536e28ee1c
https://github.com/llvm/llvm-project/commit/3377b56338d93760507e1707ebde48536e28ee1c
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
R clang/lib/Driver/ToolChains/Managarm.cpp
R clang/lib/Driver/ToolChains/Managarm.h
M clang/lib/Lex/InitHeaderSearch.cpp
R clang/test/Driver/Inputs/basic_managarm_tree/lib/aarch64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/lib/riscv64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/lib/x86_64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/lib64/aarch64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/lib64/riscv64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/lib64/x86_64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/include/aarch64-managarm-mlibc/c++/10/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/10/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/v1/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/include/riscv64-managarm-mlibc/c++/10/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/include/x86_64-managarm-mlibc/c++/10/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/aarch64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbegin.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginS.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginT.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbegin.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginS.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginT.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbegin.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginS.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginT.o
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/riscv64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/x86_64-managarm-mlibc/.keep
R clang/test/Driver/Inputs/basic_managarm_tree/usr/lib64/.keep
R clang/test/Driver/managarm.cpp
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-macros-no-warnings.c
Log Message:
-----------
Revert "[clang] Add managarm support" (#144514)
Reverts llvm/llvm-project#139271
There are multiple failing build bots:
https://lab.llvm.org/buildbot/#/builders/10/builds/7482
https://lab.llvm.org/buildbot/#/builders/11/builds/17473
Commit: 5f841a6284900026929edcbe8d2b98ce813e0bbc
https://github.com/llvm/llvm-project/commit/5f841a6284900026929edcbe8d2b98ce813e0bbc
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/include/flang/Support/OpenMP-features.h
M flang/test/Driver/flang-openmp-version-macro.f90
Log Message:
-----------
[flang][OpenMP] Set _OPENMP macro for version 6.0 (#144410)
Commit: b91936aeffb798b7deb67aff7bc5c84acea5452e
https://github.com/llvm/llvm-project/commit/b91936aeffb798b7deb67aff7bc5c84acea5452e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
Log Message:
-----------
AMDGPU: Combine nnan fminimum/fmaximum to fminnum_ieee/fmaxnum_ieee (#142217)
This improves codegen for gfx950, where fminimum/fmaximum are
legal through fminimum3/fmaximum3, so may have an additional
encoding cost.
Commit: b4e39e4ff923334a8a1fdcc6d92b01d3885a01f2
https://github.com/llvm/llvm-project/commit/b4e39e4ff923334a8a1fdcc6d92b01d3885a01f2
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[LLVM] [Support] Query the terminal width using `ioctl()` (#143514)
On unix systems, we were trying to determine the terminal width using
the `COULMNS` environment variable. Unfortunately, `COLUMNS` is not
exported by all shells and thus not available on some systems.
We were previously using `ioctl()` for this; fall back to doing so if `COLUMNS`
does not exist or does not store a positive integer.
This essentially reverts a3eb3d3d92d037fe3c9deaad87f6fc42fe9ea766 and
parts of https://reviews.llvm.org/D61326.
For more information, see #139499.
Fixes #139499.
Commit: 3451cd5d206f29df5b6ab5c200b7b8b17f3f2e3f
https://github.com/llvm/llvm-project/commit/3451cd5d206f29df5b6ab5c200b7b8b17f3f2e3f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
Log Message:
-----------
[PowerPC] Regenerate MIR test checks (NFC)
Commit: 76ea1db1746db254716aafbc992b637cd10c6ea3
https://github.com/llvm/llvm-project/commit/76ea1db1746db254716aafbc992b637cd10c6ea3
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
Log Message:
-----------
[PowerPC] Split test into assembly and MIR variants (NFC)
So that both can be generated.
Commit: 977d8a4bcd83797217433709201922b9deb97ae2
https://github.com/llvm/llvm-project/commit/977d8a4bcd83797217433709201922b9deb97ae2
Author: Vincent <llvm at viceroygroup.ca>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Scope.h
M clang/lib/Sema/SemaExpr.cpp
A clang/test/Sema/gh87867.c
Log Message:
-----------
[clang][Sema] Fixed Compound Literal is not Constant Expression (#143852)
Added a check for a compound literal hiding inside a function.
fixes #87867
Commit: 816ab1af0da1dc833f487933e7d6fb470d844001
https://github.com/llvm/llvm-project/commit/816ab1af0da1dc833f487933e7d6fb470d844001
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFCI][TableGen][DecoderEmitter] Cull Op handling when possible (#142974)
TryDecode/CheckPredicate/SoftFail MCD ops are not used by many targets.
Track the set of opcodes that were emitted and emit code for handling
TryDecode/CheckPredicate/SoftFail ops when decoding only if there were
emitted. This is purely eliminating dead code in the generated
`decodeInstruction` function.
This results in the following reduction in the size of the Disassembler
.so files with a release x86_64 release build on Linux:
```
Target Old Size New Size % reduction
build/lib/libLLVMAArch64Disassembler.so.21.0git 256656 256656 0.00
build/lib/libLLVMAMDGPUDisassembler.so.21.0git 813000 808168 0.59
build/lib/libLLVMARCDisassembler.so.21.0git 44816 43536 2.86
build/lib/libLLVMARMDisassembler.so.21.0git 281744 278808 1.04
build/lib/libLLVMAVRDisassembler.so.21.0git 36040 34496 4.28
build/lib/libLLVMBPFDisassembler.so.21.0git 26248 23168 11.73
build/lib/libLLVMCSKYDisassembler.so.21.0git 55960 53632 4.16
build/lib/libLLVMHexagonDisassembler.so.21.0git 115952 113416 2.19
build/lib/libLLVMLanaiDisassembler.so.21.0git 24360 21008 13.76
build/lib/libLLVMLoongArchDisassembler.so.21.0git 58584 56168 4.12
build/lib/libLLVMM68kDisassembler.so.21.0git 57264 53880 5.91
build/lib/libLLVMMSP430Disassembler.so.21.0git 28896 28440 1.58
build/lib/libLLVMMipsDisassembler.so.21.0git 123128 120568 2.08
build/lib/libLLVMPowerPCDisassembler.so.21.0git 80656 78096 3.17
build/lib/libLLVMRISCVDisassembler.so.21.0git 154080 150200 2.52
build/lib/libLLVMSparcDisassembler.so.21.0git 42040 39568 5.88
build/lib/libLLVMSystemZDisassembler.so.21.0git 97056 94552 2.58
build/lib/libLLVMVEDisassembler.so.21.0git 83944 81352 3.09
build/lib/libLLVMWebAssemblyDisassembler.so.21.0git 25280 25280 0.00
build/lib/libLLVMX86Disassembler.so.21.0git 2920624 2920624 0.00
build/lib/libLLVMXCoreDisassembler.so.21.0git 48320 44288 8.34
build/lib/libLLVMXtensaDisassembler.so.21.0git 42248 35840 15.17
```
Commit: 9fed480f183d9cfa784228cd77b2c0a642fca697
https://github.com/llvm/llvm-project/commit/9fed480f183d9cfa784228cd77b2c0a642fca697
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/callcont-fallthru.s
Log Message:
-----------
[BOLT] Explicitly check for returns when extending call continuation profile (#143295)
Call continuation logic relies on assumptions about fall-through origin:
- the branch is external to the function,
- fall-through start is at the beginning of the block,
- the block is not an entry point or a landing pad.
Leverage trace information to explicitly check whether the origin is a
return instruction, and defer to checks above only in case of
DSO-external branch source.
This covers both regular and BAT cases, addressing call continuation
fall-through undercounting in the latter mode, which improves BAT
profile quality metrics. For example, for one large binary:
- CFG discontinuity 21.83% -> 0.00%,
- CFG flow imbalance 10.77%/100.00% -> 3.40%/13.82% (weighted/worst)
- CG flow imbalance 8.49% —> 8.49%.
Depends on #143289.
Test Plan: updated callcont-fallthru.s
Commit: 917bc909673a491fe070fe41c4ad112bcffd4c06
https://github.com/llvm/llvm-project/commit/917bc909673a491fe070fe41c4ad112bcffd4c06
Author: William Moses <gh at wsmoses.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
Log Message:
-----------
[MLIR][LLVMIR] Mark Funcop as affinescope (#144456)
All functions are conceptually an affine scope.
Commit: de3339063ae5a926ab2ed17651a0e628b9c34fb0
https://github.com/llvm/llvm-project/commit/de3339063ae5a926ab2ed17651a0e628b9c34fb0
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/config.bzl
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
[bazel] Port b4e39e4ff923334a8a1fdcc6d92b01d3885a01f2
Commit: dc72b91ffedf791a44a1af19b00064a2a3c59ab9
https://github.com/llvm/llvm-project/commit/dc72b91ffedf791a44a1af19b00064a2a3c59ab9
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
Log Message:
-----------
[AArch64] Report icmp as free if it can be folded into ands (#143286)
Since changing the backend to fold x >= 1 / x < 1 -> x > 0 / x <= 0 and
x <= -1 / x > -1 -> x > 0 / x <= 0, this should be reflected in the
cost.
Commit: 414710c753d87d314529857e15d1ad01a76c6605
https://github.com/llvm/llvm-project/commit/414710c753d87d314529857e15d1ad01a76c6605
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/isCommutative.ll
Log Message:
-----------
[SLP] Fix isCommutative to check uses of the original instruction instead of the converted instruction. (#143094)
Commit: 35f6d917206d79ab0e3d382a36ca05ccc13983d5
https://github.com/llvm/llvm-project/commit/35f6d917206d79ab0e3d382a36ca05ccc13983d5
Author: Richard Howell <rmaz at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lld/MachO/DriverUtils.cpp
A lld/test/MachO/reexport-with-symlink.s
Log Message:
-----------
[lld] check cache in loadDylib before real_path (#143595)
Commit: 0a7b0c844c59189ad4f5072b73d7dfdfd78e76b7
https://github.com/llvm/llvm-project/commit/0a7b0c844c59189ad4f5072b73d7dfdfd78e76b7
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.cpp
M lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.h
M lldb/test/API/tools/lldb-dap/save-core/TestDAP_save_core.py
Log Message:
-----------
[lldb][Expression] Remove IR pointer checker (#144483)
Currently when jitting expressions, LLDB scans the IR instructions of
the `$__lldb_expr` and will insert a call to a utility function for each
load/store instruction. The purpose of the utility funciton is to
dereference the load/store operand. If that operand was an invalid
pointer the utility function would trap and LLDB asks the IR checker
whether it was responsible for the trap, in which case it prints out an
error message saying the expression dereferenced an invalid pointer.
This is a lot of setup for not much gain. In fact, creating/running this
utility expression shows up as ~2% of the expression evaluation time
(though we cache them for subsequent expressions). And the error message
we get out of it is arguably less useful than if we hadn't instrumented
the IR. It was also untested.
Before:
```
(lldb) expr int a = *returns_invalid_ptr()
error: Execution was interrupted, reason: Attempted to dereference an invalid pointer..
The process has been returned to the state before expression evaluation.
```
After:
```
(lldb) expr int a = *returns_invalid_ptr()
error: Expression execution was interrupted: EXC_BAD_ACCESS (code=1, address=0x5).
The process has been returned to the state before expression evaluation.
```
This patch removes this IR checker.
Commit: 8f797542258f6e682eb251d0851922a1ac08fb44
https://github.com/llvm/llvm-project/commit/8f797542258f6e682eb251d0851922a1ac08fb44
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll
Log Message:
-----------
[SCEV] Better preserve wrapping info in SimplifyICmpOperands for UGE. (#144404)
Update SimplifyICmpOperands to only try subtracting 1 from RHS first, if
RHS is an op we can fold the subtract directly into. Otherwise try
adding to LHS first, as we can preserve NUW flags.
This improves results in a few cases, including the modified test case
from berkeley-abc and new code to be added in
https://github.com/llvm/llvm-project/pull/128061.
Note that there are more cases where the results can be improved by
better ordering here which I'll try to investigate as follow-up.
PR: https://github.com/llvm/llvm-project/pull/144404
Commit: 0fb198e132eff36281a20698588d815c3c30f991
https://github.com/llvm/llvm-project/commit/0fb198e132eff36281a20698588d815c3c30f991
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/horizontal-sum.ll
Log Message:
-----------
[X86] Remove combineShuffleOfConcatUndef fold (#144524)
We can now let a mixture of combineConcatVectorOps and target shuffle combining handle this instead of creating ISD::CONCAT_VECTORS nodes and hoping they will merge properly.
In the horizontal-sum.ll test changes we were creating a ISD::CONCAT_VECTORS node that was being split shortly after, but not before causing issues with HADD folding due to additional uses.
Commit: 4cfe0d7f4c2c39dd90e27258aa448789f2ba4278
https://github.com/llvm/llvm-project/commit/4cfe0d7f4c2c39dd90e27258aa448789f2ba4278
Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
A flang/test/Lower/OpenMP/copyprivate5.f90
Log Message:
-----------
[flang][OpenMP] Support using copyprivate with fir.boxchar arguments (#144092)
Implement the lowering for passing a fir.boxchar argument to the
copyprivate clause.
Resolves https://github.com/llvm/llvm-project/issues/142123.
---------
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Commit: 549bc55cc39bb9fb22df464bcf3b7d4d4a5ff507
https://github.com/llvm/llvm-project/commit/549bc55cc39bb9fb22df464bcf3b7d4d4a5ff507
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/CMakeLists.txt
M mlir/test/Target/SPIRV/constant.mlir
M mlir/test/lit.cfg.py
A mlir/test/lit.local.cfg
M mlir/test/lit.site.cfg.py.in
Log Message:
-----------
[mlir][spirv] Fix int type declaration duplication when serializing (#143108)
At the MLIR level unsigned integer and signless integers are different
types. Indeed when looking up the two types in type definition cache
they do not match.
Hence when translating a SPIR-V module which contains both usign and
signless integers will contain the same type declaration twice
(something like OpTypeInt 32 0) which is not permitted in SPIR-V and
such generated modules fail validation.
This patch solves the problem by mapping unisgned integer types to
singless integer types before looking up in the type definition cache.
---------
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 7ec103a984ff114d24f26d935fe2292379269b53
https://github.com/llvm/llvm-project/commit/7ec103a984ff114d24f26d935fe2292379269b53
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Port #143108 to bazel (#144538)
Commit: 9eb0020555fc643582b2802abb8c1bc92059c248
https://github.com/llvm/llvm-project/commit/9eb0020555fc643582b2802abb8c1bc92059c248
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/DemandedBits.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/ADCE.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Evaluator.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Remove a swathe of debug-intrinsic code (#144389)
Seeing how we can't generate any debug intrinsics any more: delete a
variety of codepaths where they're handled. For the most part these are
plain deletions, in others I've tweaked comments to remain coherent, or
added a type to (what was) type-generic-lambdas.
This isn't all the DbgInfoIntrinsic call sites but it's most of the
simple scenarios.
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: c9a87a50aee3c91f36d33c170d5131bcc370c289
https://github.com/llvm/llvm-project/commit/c9a87a50aee3c91f36d33c170d5131bcc370c289
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Log Message:
-----------
[SLPVectorizer] Use accurate cost for external users of resize shuffles (#137419)
When implementing the vectorization, we potentially need to add shuffles
for external users. In such cases, we may be shuffling a smaller vector
into a larger vector. When this happens `ResizeToVF` will just build a
poison padded identity vector. Then the to build the final shuffle, we
just use the `SK_InsertSubvector` mask.
This is possibly clearer by looking at the included test in
SLPVectorizer/AMDGPU/external-shuffle.ll
In the exit block we have a bunch of shuffles to glue the vectorized
tree match the `InsertElement` users. `TMP25` holds the result of
resizing the v2i16 vectorized sequence to match the `InsertElement` size
v16i16. Then `TMP26` is the final shuffle which replaces the
`InsertElement` sequence. This is just an insertsubvector.
However, when calculating the cost for these shuffles, we aren't
modelling this correctly. `ResizeToVF` will indicate to
`performExtractsShuffleAction` that we cannot use the original mask due
to the resize shuffle. The consequence is that the cost calculation uses
a different shuffle mask than what is ultimately used.
Going back to the included test, we can consider again `TMP26`. Clearly
we can see the shuffle uses a mask {0, 1, 2, 3, 16, 17, poison ..}.
However, we will currently calculate the cost with a mask {0, 1, 2, 3,
20, 21, ...} we have replaced 16 and 17 with 20 and 21 (Index + Vector
Size). Queries like BasicTTImpl::improveShuffleKindFromMask will not
recognize this as an `SK_InsertSubvector` mask, and targets which have
reduced costs for `SK_InsertSubvector` will not accurately calculate the
cost.
Commit: 02b78ff9c639993356ccc72b847128fd1ff7f2ba
https://github.com/llvm/llvm-project/commit/02b78ff9c639993356ccc72b847128fd1ff7f2ba
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Option/OptSpecifier.h
M llvm/include/llvm/Transforms/IPO.h
M llvm/include/llvm/Transforms/Utils/PromoteMemToReg.h
Log Message:
-----------
[llvm] include Compiler.h in a few headers where it was missed (#144464)
Add missing `#include "llvm/Support/Compiler.h"` in a few LLVM headers
that use the `LLVM_ABI` macro.
Commit: 14286244f1dca9300ead8bf83f049df2ffa97180
https://github.com/llvm/llvm-project/commit/14286244f1dca9300ead8bf83f049df2ffa97180
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/IROutliner.cpp
Log Message:
-----------
Follow up to 9eb0020555, squelch unused variable warning
It turns out that this now-deleted debug-intrinsic code was the only use of
CI.
Commit: 1410e69b641182e942470a90d4a0bb5a2910805f
https://github.com/llvm/llvm-project/commit/1410e69b641182e942470a90d4a0bb5a2910805f
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
A llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
Log Message:
-----------
[SPIRV] Allow __spirv_SpecConstant in Vulkan shaders (#143543)
There is a builtin __spirv_SpecConstant that the SPIR-V backend expands
into a specialization constant. However, it is currently only enable for
OpenCL shaders, and not the graphic shaders.
We want to use it for specialization constants coming from HLSL, so we
are enabling it for graphic shaders as well.
Implements https://github.com/llvm/wg-hlsl/pull/287
Fixes https://github.com/llvm/llvm-project/issues/142991
Commit: c80282d333d7248c8a34694ce1bec9a40681c1c5
https://github.com/llvm/llvm-project/commit/c80282d333d7248c8a34694ce1bec9a40681c1c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)
The hardware min/max follow the IR rules with IEEE mode disabled,
so we can avoid the canonicalizes of the input. We lose the quieting
of a signaling nan if both inputs are nans, but we only require that
with strictfp.
Commit: 72fb8ae541dcb6d4ab24283bd91a1fc64a9b7e3b
https://github.com/llvm/llvm-project/commit/72fb8ae541dcb6d4ab24283bd91a1fc64a9b7e3b
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lld/test/ELF/lto/aarch64-pac-got-func.ll
Log Message:
-----------
[lld][test][PAC] Do not rely on concrete offsets in LTO tests (#143358)
When changing codegen (e.g. in #130809), offsets in binaries produced by
LTO tests might change. We do not need to match concrete offset values,
it's enough to ensure that hex values in particular places are
identical.
---------
Co-authored-by: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Commit: 4ced29b8482e3537da7d27d410bf7947b0666b4c
https://github.com/llvm/llvm-project/commit/4ced29b8482e3537da7d27d410bf7947b0666b4c
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.cpp
Log Message:
-----------
[lldb][Expression] Don't create Objective-C IR checker for pure-C++ targets/frames (#144503)
There's no need to create this utility function (and run it) for
targets/frames that aren't Objective-C/Objective-C++.
Commit: a5f5f1209aa122ee295ae0dc0f1ee594ad988ecd
https://github.com/llvm/llvm-project/commit/a5f5f1209aa122ee295ae0dc0f1ee594ad988ecd
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Use subtarget feature for v_lshl_add_u64 pattern. NFC. (#144544)
Following on from #133723, use the new subtarget feature for the
selection pattern as well as for the instruction definition.
Commit: cd4e3843395329538feb1c29cd582471b482caf7
https://github.com/llvm/llvm-project/commit/cd4e3843395329538feb1c29cd582471b482caf7
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/test/Semantics/modfile75.F90
Log Message:
-----------
[flang][test] Removed temporary workaround for buildbots.
Commit: cf637b7e3554976419a0d672ad4c252137dc34f3
https://github.com/llvm/llvm-project/commit/cf637b7e3554976419a0d672ad4c252137dc34f3
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/parallel-sections01.f90
A flang/test/Semantics/OpenMP/sections-goto.f90
M flang/test/Semantics/OpenMP/sections02.f90
Log Message:
-----------
[flang][OpenMP] Fix goto within SECTION (#144502)
Previously we didn't push any context for SECTION and they are not
modelled with differing scopes and so goto detection couldn't tell that
GOTOs between two SECTIONs were between constructs rather than just
staying inside of the parent SECTIONS construct.
Fixes #143231
Commit: 0108a5908cab5e418c683ef9b6e1810755344b5e
https://github.com/llvm/llvm-project/commit/0108a5908cab5e418c683ef9b6e1810755344b5e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
Log Message:
-----------
[SLP]Fix a crash on an subvector size calculation for non-power-of-2 vector
Patch fixes cost estimation for the extractelements from non-power-of-2
vectors, defined as subvector extracts. In this case the subvector size
might be not adjusted to a whole register size, need to get the minimum
between whole vector size and the actual difference to prevent compiler
crash.
Fixes #143513
Commit: 00139f10c3cd4118de7148635c820bb42843287a
https://github.com/llvm/llvm-project/commit/00139f10c3cd4118de7148635c820bb42843287a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/bug26185.ll
M llvm/test/CodeGen/NVPTX/i1-ext-load.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
Log Message:
-----------
[NVPTX] Cleanup ld/st lowering (#143936)
Commit: eb31c422d0dc816bf285a81bf92690d4d16273ed
https://github.com/llvm/llvm-project/commit/eb31c422d0dc816bf285a81bf92690d4d16273ed
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/aarch64-gnutools.c
A clang/test/Driver/aarch64-toolchain-extra.c
A clang/test/Driver/aarch64-toolchain.c
A clang/test/Driver/arm-gnutools.c
A clang/test/Driver/arm-toolchain-extra.c
A clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
A clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
[Driver] Add support for GCC installation detection in Baremetal toolchain (#121829)
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is derived from those locations.
- If not, the logic falls back to the existing sysroot inference
mechanism already present in the Baremetal toolchain.
- Support for adding include paths for the libstdc++ library has also
been added.
Additionally, the restriction to always use the integrated assembler has
been removed. With a valid GCC installation, the GNU assembler can now
be used as well.
This patch currently updates and adds tests for the ARM target only.
RISC-V-specific tests will be introduced in a later patch, once the
RISCVToolChain is fully merged into the Baremetal toolchain. At this
stage, there is no way to test the RISC-V target within this PR.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: e6a41399cb8796e5d18940d49b0151704568321a
https://github.com/llvm/llvm-project/commit/e6a41399cb8796e5d18940d49b0151704568321a
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libc/src/__support/wchar/character_converter.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/wchar/CMakeLists.txt
A libc/test/src/__support/wchar/utf8_to_32_test.cpp
Log Message:
-----------
Reland "[libc] utf8 to 32 CharacterConverter" (#144450)
Reverts llvm/llvm-project#144446
Figured out the issue, so creating a new pull request.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 65d590e8d012df9dabbf8b3ec929fd1543c7398a
https://github.com/llvm/llvm-project/commit/65d590e8d012df9dabbf8b3ec929fd1543c7398a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineLogicBlendIntoConditionalNegate - convert to SDPatternMatch matching. NFC. (#144536)
Commit: c66be289901b3f035187d391e80e3610d7d6232e
https://github.com/llvm/llvm-project/commit/c66be289901b3f035187d391e80e3610d7d6232e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Allocate IntegralAP and Floating types using an allocator (#144246)
Both `APInt` and `APFloat` will heap-allocate memory themselves using
the system allocator when the size of their data exceeds 64 bits.
This is why clang has `APNumericStorage`, which allocates its memory
using an allocator (via `ASTContext`) instead. Calling `getValue()` on
an ast node like that will then create a new `APInt`/`APFloat` , which
will copy the data (in the `APFloat` case, we even copy it twice).
That's sad but whatever.
In the bytecode interpreter, we have a similar problem. Large integers
and floating-point values are placement-new allocated into the
`InterpStack` (or into the bytecode, which is a `vector<std::byte>`).
When we then later interrupt interpretation, we don't run the destructor
for all items on the stack, which means we leak the memory the
`APInt`/`APFloat` (which backs the `IntegralAP`/`Floating` the
interpreter uses).
Fix this by using an approach similar to the one used in the AST. Add an
allocator to `InterpState`, which is used for temporaries and local
values. Those values will be freed at the end of interpretation. For
global variables, we need to promote the values to global lifetime,
which we do via `InitGlobal` and `FinishInitGlobal` ops.
Interestingly, this results in a slight _improvement_ in compile times:
https://llvm-compile-time-tracker.com/compare.php?from=6bfcdda9b1ddf0900f82f7e30cb5e3253a791d50&to=88d1d899127b408f0fb0f385c2c58e6283195049&stat=instructions:u
(but don't ask me why).
Fixes https://github.com/llvm/llvm-project/issues/139012
Commit: 9ec75a50bc48c84c68430f113332769d23481ef5
https://github.com/llvm/llvm-project/commit/9ec75a50bc48c84c68430f113332769d23481ef5
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsTargetObjectFile.cpp
Log Message:
-----------
MIPS: Replace MipsMCExpr with MCSpecifierExpr
Commit: 382e3fdbb476a5d5771b315daedcd05a15883fbc
https://github.com/llvm/llvm-project/commit/382e3fdbb476a5d5771b315daedcd05a15883fbc
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
Log Message:
-----------
[lldb][Formatter] Get element type for unordered_maps from __hash_table::value_type (#144517)
https://github.com/llvm/llvm-project/pull/143501 changes usage of
`__hash_value_type` in libcxx to an empty tag type. This type will no
longer have a definition in DWARF. Currently the LLDB unordered_map
formatter deduces the map's `element_type` by looking at the `__cc_`
member of `__hash_value_type`. But that will no longer work because we
only have its forward declaration. Since what we're really after is the
type that `__hash_value_type` is wrapping, we can just look at the
`__hash_table::value_type` typedef. With
https://github.com/llvm/llvm-project/pull/143501 that will now point to
the `std::pair` element type (which used to be what we got from
`__cc_`).
TBD: need to double-check this works for older layouts. Quick glance at
the code makes me suspicious of cases like `unordered_map<std::pair<int,
int>, int>`
Commit: 4e884dd993e040f7ccd83ecdc3c4570d23a42ee6
https://github.com/llvm/llvm-project/commit/4e884dd993e040f7ccd83ecdc3c4570d23a42ee6
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
R llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp
Log Message:
-----------
SPARC: Remove SparcMCExpr.h
Commit: 0c608175c11cf0ce797be7575a7c8d8ebcdecbd8
https://github.com/llvm/llvm-project/commit/0c608175c11cf0ce797be7575a7c8d8ebcdecbd8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] matchLogicBlend - convert to SDPatternMatch matching. NFC. (#144546)
Removes a LOT of commutative matching.
Commit: b14e03d8555043bc35e9c75fff7f52d28950b3ab
https://github.com/llvm/llvm-project/commit/b14e03d8555043bc35e9c75fff7f52d28950b3ab
Author: nerix <nerixdev at outlook.de>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.cpp
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.h
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string/TestDataFormatterLibcxxString.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string_view/TestDataFormatterLibcxxStringView.py
Log Message:
-----------
[LLDB] Consolidate C++ string buffer summaries (#144258)
As part of https://github.com/llvm/llvm-project/pull/143177, I moved the
non-libc++ specific formatting of `std::string`s out to `CxxStringTypes`
as MSVC's STL `std::string` can also be thought of a pointer+size pair.
I named this kind of string "string buffer".
This PR picks that change, so the MSVC PR can be smaller.
Unfortunately, libstdc++'s `std::string` does not fit this (it also uses
a different string printer function).
This resolves two FIXMEs in the libc++ tests, where empty u16 and u32
strings didn't have any prefix (u/U).
Commit: 5baf351ba819e1e6bae0250492e85a2862ef406b
https://github.com/llvm/llvm-project/commit/5baf351ba819e1e6bae0250492e85a2862ef406b
Author: yonghong-song <yhs at fb.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
Log Message:
-----------
[BPF] Do not allow gotol in the middle of asm insn (#144545)
Previously I accidentally allowed 'gotol' insn in the middle of asm insn
([1]). But actually 'gotol' is not allowed in the middle of any asm
insn, so remove it from isValidIdInMiddle().
[1] https://github.com/yonghong-song/llvm-project/commit/6c412b6c6faa2dabd8602d35d3f5e796fb1daf80
Commit: 556e69b7f4328a0d7c36c9d7ca0dd8f52f82ad71
https://github.com/llvm/llvm-project/commit/556e69b7f4328a0d7c36c9d7ca0dd8f52f82ad71
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/cmake/modules/FindPythonAndSwig.cmake
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] make lit use the same Python executable for building and testing (#143756)
When testing LLDB, we want to make sure to use the same Python as the
one we used to build it.
This patch uses the CMake variable `Python3_ROOT_DIR` to add the correct
Python to the `PATH` in LLDB lit tests, in order to ensure of this.
Please see https://github.com/swiftlang/swift/pull/82063 for the
original issue.
This is a continuation of https://github.com/swiftlang/swift/pull/82063.
Commit: 8063bd153c6aca43869d96aee64aeceb9be98ca5
https://github.com/llvm/llvm-project/commit/8063bd153c6aca43869d96aee64aeceb9be98ca5
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
A mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir
Log Message:
-----------
[MLIR][XeGPU] Add support for elementwise ops in Wg to Sg distribute pass [1/N] (#142797)
This PR adds support for Elementwise operations' (unary & binary)
lowering from Workgroup to Subgroup.
Commit: 01a7a21a4b8070a88e5dcc9753066e38d26faf85
https://github.com/llvm/llvm-project/commit/01a7a21a4b8070a88e5dcc9753066e38d26faf85
Author: Chris B <chris.bieneman at me.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
Log Message:
-----------
[CMake] Add BINARY_DIR argument for add_lit_testsuites (#144431)
We're doing some slightly odd things with LIT in the offload-test-suite.
Specifically we generate multiple binary directories to configure and
run tests with different configurations from the same source root.
In this configuration the subdirectory targets need to instead point to
the correct generated binary directory and use test filtering to get a
subset of tests.
Commit: 526310e916af2073e30b57b678307ce94df803f3
https://github.com/llvm/llvm-project/commit/526310e916af2073e30b57b678307ce94df803f3
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/test/Transforms/GVN/opt-remarks.ll
Log Message:
-----------
[Remarks] Elaborate on called intrinsics (#143985)
Commit: ec230aa7a7d13c222c0b34b87c3c16937383b4a0
https://github.com/llvm/llvm-project/commit/ec230aa7a7d13c222c0b34b87c3c16937383b4a0
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[Driver] Add support for crtbegin.o, crtend.o and libgloss lib to BareMetal toolchain object (#121830)
This patch conditionalise the addition of crt{begin,end}.o object files
along
with addition of -lgloss lib based on whether libc selected is newlib or
llvm
libc. Since there is no way a user can specify which libc it wants to
link
against, currently passing valid GCCInstallation to driver will select
newlib
otherwise it will default to llvm libc.
Moreover, this patch makes gnuld the default linker for baremetal
toolchain
object. User need to pass `-fuse-ld=lld` explicitly to driver to select
lld
This is the 2nd patch in the series of patches of merging RISCVToolchain
into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 8513066f2c49457f5d1f63e275403330f854041c
https://github.com/llvm/llvm-project/commit/8513066f2c49457f5d1f63e275403330f854041c
Author: someoneinjd <someoneinjd at outlook.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
A clang-tools-extra/clangd/test/positionencoding.test
Log Message:
-----------
[clangd] Implement LSP 3.17 positionEncoding (#142903)
This PR adds support for the `positionEncoding` client capability
introduced in LSP 3.17. Clangd can now negotiate the position encoding
with the client during initialization.
Fix https://github.com/clangd/clangd/issues/1746
Co-authored-by: kadir çetinkaya <kadircetinkaya.06.tr at gmail.com>
Commit: 9dd1c66e8ffba73fead13aaf359e290f6e1d4899
https://github.com/llvm/llvm-project/commit/9dd1c66e8ffba73fead13aaf359e290f6e1d4899
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
Log Message:
-----------
[VPlan] Expand VPWidenIntOrFpInductionRecipe into separate recipes (#118638)
The motivation of this PR is to make #115274 easier to implement, and
should allow us to add EVL support by just passing EVL to the VF
operand.
The current difficulty with widening IVs with EVL is that
VPWidenIntOrFpInductionRecipe generates its own backedge value. Since
it's a VPHeaderPHIRecipe the VF operand must be in the preheader, which
means we can't use the EVL since it's defined in the loop body.
The gist in this PR is to take the approach in #114305 and expand
VPWidenIntOrFpInductionRecipe into several recipes for the initial
value, phi and backedge value just before execution. I.e. this example:
```
vector.ph:
Successor(s): vector loop
<x1> vector loop: {
vector.body:
WIDEN-INDUCTION %i = phi %start, %step, %vf
...
EMIT branch-on-count ...
No successors
}
```
gets expanded to:
```
vector.ph:
...
vp<%induction.start> = ...
vp<%induction.increment> = ...
Successor(s): vector loop
<x1> vector loop: {
vector.body:
ir<%i> = WIDEN-PHI vp<%induction.start>, vp<%vec.ind.next>
...
vp<%vec.ind.next> = add ir<%i>, vp<%induction.increment>
EMIT branch-on-count ...
No successors
}
```
This allows us to a value defined in the loop in the backedge value, and
also means we can just reuse the existing backedge fixups in
VPlan::execute without having to specially handle it ourselves.
After this #115274 should just become a matter of setting the VF operand
to EVL (and building the increment step in the loop body, not the
preheader).
Commit: 9e0186d925f0c375a627866c59394f25c22eb3ff
https://github.com/llvm/llvm-project/commit/9e0186d925f0c375a627866c59394f25c22eb3ff
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/unittests/Frontend/CMakeLists.txt
A llvm/unittests/Frontend/HLSLRootSignatureRangesTest.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement `ResourceRange` as an `IntervalMap` (#140957)
A resource range consists of a closed interval, `[a;b]`, denoting which
shader registers it is bound to.
For instance:
- `CBV(b1)` corresponds to the resource range of `[1;1]`
- `CBV(b0, numDescriptors = 3)` likewise to `[0;2]`
We want to provide an error diagnostic when there is an overlap in the
required registers (an overlap in the resource ranges).
The goal of this pr is to implement a structure to model a set of
resource ranges and provide an api to detect any overlap over a set of
resource ranges.
`ResourceRange` models this by implementing an `IntervalMap` to denote a
mapping from an interval of registers back to a resource range. It
allows for a new `ResourceRange` to be added to the mapping and it will
report if and what the first overlap is.
For the context of how this will be used in validation of a
`RootSignatureDecl` please see the proceeding pull request here:
https://github.com/llvm/llvm-project/pull/140962.
- Implements `ResourceRange` as an `IntervalMap`
- Adds unit testing of the various `insert` scenarios
Note: it was also considered to implement this as an `IntervalTree`,
this would allow reporting of a diagnostic for each overlap that is
encountered, as opposed to just the first. However, error generation of
just reporting the first error is already rather verbose, and adding the
additional diagnostics only made this worse.
Part 1 of https://github.com/llvm/llvm-project/issues/129942
Commit: ed07b54b38c675235b4ce1bfd49e1fff372f6520
https://github.com/llvm/llvm-project/commit/ed07b54b38c675235b4ce1bfd49e1fff372f6520
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
Log Message:
-----------
[CIR][NFCI] Represent Complex RValues As Single Value (#144519)
This patch removes one mlir::Value in the RValue class that has been
used to represent complex values in classic CG. In CIR we plan on
representing complex as a single value. It also removes some now
unnecessary member functions related to complex handling.
Commit: 3a06e9a710b7cfdbf1c002acc46fa76617e8baf8
https://github.com/llvm/llvm-project/commit/3a06e9a710b7cfdbf1c002acc46fa76617e8baf8
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
Conditionalise the addition of Aarch64 function Multi versioning support on aarch64 target (#143749)
Currently, `ENABLE_BAREMETAL_AARCH64_FMV` is added to builtin defines
for all baremetal targets though it is only needed for aarch64. This
patch fixes this by adding it only for aarch64 target.
Commit: 7ea710fafa5782a274ded2ab6933c63c5c71f2ee
https://github.com/llvm/llvm-project/commit/7ea710fafa5782a274ded2ab6933c63c5c71f2ee
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/rename_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/strtold_test.cpp
Log Message:
-----------
Fix/reapply "[libc] Migrate stdio tests to ErrnoCheckingTest. (#144134)
This reverts commit 92a116c4ef822950f8c57eaa5164c844c73a1f7e with a fix
for fgets test - convert nullptr to fgets return type (char*), since the
matcher is pedantic.
Commit: 4943e746909ddbf8845e7fa397a97b918bf777df
https://github.com/llvm/llvm-project/commit/4943e746909ddbf8845e7fa397a97b918bf777df
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
Log Message:
-----------
fixup! [Remarks] Elaborate on called intrinsics (#143985)
Commit: 030b5519ec139757c13a6d6f337e69750ec24d6e
https://github.com/llvm/llvm-project/commit/030b5519ec139757c13a6d6f337e69750ec24d6e
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing deps for XeGPUTransforms
Commit: b876b3fa98cffd5b8755398f9a8218f667464d76
https://github.com/llvm/llvm-project/commit/b876b3fa98cffd5b8755398f9a8218f667464d76
Author: vitor1001 <56533861+vitor1001 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Headers/__clang_cuda_intrinsics.h
Log Message:
-----------
Add missing intrinsics to cuda headers (#143664)
LLVM prevents the sm_32_intrinsics.hpp header from being included with a
#define __SM_32_INTRINSICS_HPP__. It also provides drop-in replacements
of the functions defined in the CUDA header.
One issue is that some intrinsics were added after the replacement was
written, and thus have no replacement, breaking code that calls them
(Raft is one example).
This patch adds the missing intrinsics.
Commit: 0cfc59ff51720ee60a71dd34077fc161886a3701
https://github.com/llvm/llvm-project/commit/0cfc59ff51720ee60a71dd34077fc161886a3701
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] remove extra empty space for XeGPUTransforms
Commit: e29bb9a038245320164c5890d1a75843e4a664ef
https://github.com/llvm/llvm-project/commit/e29bb9a038245320164c5890d1a75843e4a664ef
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Analysis/IR2Vec.cpp
Log Message:
-----------
[IR2Vec] Consider only reachable BBs and non-debug instructions (#143476)
Changes to consider BBs that are reachable from the entry block. Similarly we skip debug instruction while computing the embeddings.
(Tracking issue - #141817)
Commit: 31523de4b000ca254259ae3167d28922e1302648
https://github.com/llvm/llvm-project/commit/31523de4b000ca254259ae3167d28922e1302648
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal-multilib.yaml
M clang/test/Driver/baremetal-sysroot.cpp
M clang/test/Driver/baremetal.cpp
Log Message:
-----------
[Driver] Fix link order of BareMetal toolchain object (#132806)
The linker job in BareMetal toolchain object will be used by GNU ld and
lld both.
However, gnuld process the arguments in the order in which they appear
on command
line, whereas there is no such restriction with lld.
The previous order was:
LibraryPaths -> Libraries -> LTOOptions -> LinkerInputs
The new order is:
LibraryPaths -> LTOOptions -> LinkerInputs -> Libraries
LTO options need to be added before adding any linker inputs because
file format
after compile stage during LTO is bitcode which gnuld natively cannot
process.
Hence will need to pass appropriate plugins before adding any bitcode
file on the
command line.
Object files that are getting linked need to be passed before processing
any
libraries so that gnuld can appropriately do symbol resolution for the
symbols
for which no definition is provided through user code.
Similar link order is also followed by other linker jobs for gnuld such
as in
gnutools::Linker in Gnu.cpp
This is the 3rd patch in the series of patches of merging RISCVToolchain
into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 2ab9c35ea93f8557827d4cadcceb05e4eed2d30a
https://github.com/llvm/llvm-project/commit/2ab9c35ea93f8557827d4cadcceb05e4eed2d30a
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
Log Message:
-----------
[DXContainer] Update DXContainer to match D3D12 spec (#143201)
Update the descriptor range flag values in DXContainerConstants.def to
match
the Direct3D12 specification. This changes two aspects:
1. Modify the DESCRIPTOR_RANGE_FLAG macro to use direct values instead
of
bit shifts
2. Update the flag values to use hex notation and match D3D12's
D3D12_DESCRIPTOR_RANGE_FLAGS enumeration:
- DESCRIPTORS_VOLATILE: 0x1
- DATA_VOLATILE: 0x2
- DATA_STATIC_WHILE_SET_AT_EXECUTE: 0x4
- DATA_STATIC: 0x8
- DESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKS: 0x10000
3. Removed NONE value from ROOT_DESCRIPTOR_FLAG
This ensures better compatibility with the D3D12 API and makes the
values
more explicit in the code.
Requested here:
https://github.com/llvm/llvm-project/pull/138315#discussion_r2132818269
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: bb288de4e0e74f235402ff41be60dabcd57e379f
https://github.com/llvm/llvm-project/commit/bb288de4e0e74f235402ff41be60dabcd57e379f
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-minmax.ll
Log Message:
-----------
[LoopPeel] Support last iteration peeling of min/max intrinsics (#143598)
This isn't terribly useful at the moment because of the step=1
restriction but it should be functionally sound. This is mostly just
making sure the codepaths don't diverge as we make other changes.
Commit: 8cd05b88ec623018ca2c68cf2418d2beed026d27
https://github.com/llvm/llvm-project/commit/8cd05b88ec623018ca2c68cf2418d2beed026d27
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[NFC][HLSL] Move Sema work from `ParseMicrosoftRootSignatureAttributeArgs` (#143184)
This separates semantic analysis from parsing by moving `RootSignatureDecl` creation, scope storage, and lookup logic into
`SemaHLSL`.
For more context see:
https://github.com/llvm/llvm-project/issues/142834.
- Define `ActOnStartRootSignatureDecl` and `ActOnFinishRootSignatureDecl` on `SemaHLSL`
- NFC so no test changes.
Resolves: https://github.com/llvm/llvm-project/issues/142834
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 80f3a28bbe7c2e17fb4b60e974c4157ec7e1eefc
https://github.com/llvm/llvm-project/commit/80f3a28bbe7c2e17fb4b60e974c4157ec7e1eefc
Author: Justin King <jcking at wulver.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_allocator.cpp
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
Log Message:
-----------
Revert "lsan: Support free_sized and free_aligned_sized from C23" (#144575)
Reverts llvm/llvm-project#144415
Need to update approach to handle Apple platforms gracefully.
Commit: 391dafd8af9c0309f2ca75621dae1dbae307b428
https://github.com/llvm/llvm-project/commit/391dafd8af9c0309f2ca75621dae1dbae307b428
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Consolidate both copies of getLMUL1VT [nfc] (#144568)
Put one copy on RISCVTargetLowering as a static function so that both
locations can use it, and rename the method to getM1VT for slightly
improved readability.
Commit: 1f10c6a277fbc1b1c6ceb7546b001af39feb92ce
https://github.com/llvm/llvm-project/commit/1f10c6a277fbc1b1c6ceb7546b001af39feb92ce
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Matrix] Hoist more IRBuilder<>'s. NFC
Commit: b59d4cf05447fdaf3d3c859e10db0b3c892f6ec6
https://github.com/llvm/llvm-project/commit/b59d4cf05447fdaf3d3c859e10db0b3c892f6ec6
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/noop_bitcast_global_array_type.ll
Log Message:
-----------
[Reland] Adjust bit cast instruction filter for DXIL Prepare pass (#143783)
Relands https://github.com/llvm/llvm-project/pull/142678, with a new
change to remove an unnecessary gep argument, after a revert was needed
due to unforeseen bugs.
Fixes https://github.com/llvm/llvm-project/issues/139013
Commit: dd65e6e0608c3390752750a0f19bca4409603db9
https://github.com/llvm/llvm-project/commit/dd65e6e0608c3390752750a0f19bca4409603db9
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A offload/cmake/caches/AMDGPULibcBot.cmake
Log Message:
-----------
[Offload][libc] Add cmake cache AMDGPU buildbot (#144500)
An upcoming libc4GPU buildbot will be using this CMake cache file for
its build configuration.
Commit: 9cb754509608b9d9143fa17f775631bbfcce0848
https://github.com/llvm/llvm-project/commit/9cb754509608b9d9143fa17f775631bbfcce0848
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
A clang/test/Driver/baremetal-undefined-symbols.c
R clang/test/Driver/riscv-args.c
Log Message:
-----------
[Driver] Add option to force undefined symbols during linking in BareMetal toolchain object. (#132807)
Add support for `-u` option to force defined symbols. This option is
supported by both lld and gnuld.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
This is the 4th patch in the series of patches for merging
RISCVToolchain object into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 57828fec760f086b334ce0cb1c465fc559dcaea4
https://github.com/llvm/llvm-project/commit/57828fec760f086b334ce0cb1c465fc559dcaea4
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Revert "[clang][bytecode] Allocate IntegralAP and Floating types using an allocator (#144246)"
This reverts commit c66be289901b3f035187d391e80e3610d7d6232e.
This breaks the armv8-quick builder:
https://lab.llvm.org/buildbot/#/builders/154/builds/17549
Commit: 667c7860ef5cc67a94c5233ff1be9c0e113ac514
https://github.com/llvm/llvm-project/commit/667c7860ef5cc67a94c5233ff1be9c0e113ac514
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/test/CIR/CodeGen/string-literals.c
A clang/test/CIR/CodeGen/string-literals.cpp
Log Message:
-----------
[CIR] Handle global string literals as char array initializer (#144384)
This change adds the line of code needed to handle a string literal as
an initializer for a character array.
Commit: b1aa845595c4dc204dfbe0e48481572e936620fc
https://github.com/llvm/llvm-project/commit/b1aa845595c4dc204dfbe0e48481572e936620fc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/fstream
Log Message:
-----------
[libc++][NFC] Consistently qualify calls to C functions in <fstream> (#144539)
Commit: 19658d14749876cf0b6633f210c923be3709323b
https://github.com/llvm/llvm-project/commit/19658d14749876cf0b6633f210c923be3709323b
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
M llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
M llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
M llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
M llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
M llvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
M llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
M llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
M llvm/lib/Target/XCore/XCoreAsmPrinter.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/LoongArch/CMakeLists.txt
M llvm/unittests/Target/RISCV/CMakeLists.txt
M llvm/unittests/Target/SPIRV/CMakeLists.txt
M llvm/unittests/Target/VE/CMakeLists.txt
M llvm/unittests/Target/WebAssembly/CMakeLists.txt
Log Message:
-----------
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
## Purpose
This patch is one in a series of code-mods that annotate LLVM’s public
interface for export. This patch annotates the `llvm/Target` library.
These annotations currently have no meaningful impact on the LLVM build;
however, they are a prerequisite to support an LLVM Windows DLL (shared
library) build.
## Background
This effort is tracked in #109483. Additional context is provided in
[this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
A sub-set of these changes were generated automatically using the
[Interface Definition Scanner (IDS)](https://github.com/compnerd/ids)
tool, followed formatting with `git clang-format`.
The bulk of this change is manual additions of `LLVM_ABI` to
`LLVMInitializeX` functions defined in .cpp files under llvm/lib/Target.
Adding `LLVM_ABI` to the function implementation is required here
because they do not `#include "llvm/Support/TargetSelect.h"`, which
contains the declarations for this functions and was already updated
with `LLVM_ABI` in a previous patch. I considered patching these files
with `#include "llvm/Support/TargetSelect.h"` instead, but since
TargetSelect.h is a large file with a bunch of preprocessor x-macro
stuff in it I was concerned it would unnecessarily impact compile times.
In addition, a number of unit tests under llvm/unittests/Target required
additional dependencies to make them build correctly against the LLVM
DLL on Windows using MSVC.
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
Commit: 7b7b5a397da1ecb9f767df5a3a3b6076cec109f9
https://github.com/llvm/llvm-project/commit/7b7b5a397da1ecb9f767df5a3a3b6076cec109f9
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
Log Message:
-----------
[AMDGPU] Remove AsmVOP3OpSel field completely. NFCI. (#144574)
Commit: 8dcf4ba6359578c4d944b75b3f96a1fbd4fb9528
https://github.com/llvm/llvm-project/commit/8dcf4ba6359578c4d944b75b3f96a1fbd4fb9528
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Fix getAsmVOP3Base call agruments. (#144572)
https://github.com/llvm/llvm-project/pull/143465 has removed
getAsmVOP3OpSel and uses getAsmVOP3Base instead, but original
call to getAsmVOP3OpSel was using HasSrc*FloatMods and the
call to getAsmVOP3Base uses HasSrc*Mods. This does not play
well with opsel. An opsel instruction has modifiers in dag but
shall not have them in the asm string.
Commit: 73f307a5ca308d356c557734765742c26bf7ed03
https://github.com/llvm/llvm-project/commit/73f307a5ca308d356c557734765742c26bf7ed03
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
Log Message:
-----------
[HLSL] Use ExtVector for firstbit intrinsics (#142679)
Fixes https://github.com/llvm/llvm-project/issues/142430
firstbit intrinsics were using the wrong vector type which causes some
conversions to fail. This PR switches them to ExtVector which resolves
the issue
Commit: a79186c1ea62bbe0579e0b1eed4ad507966cca41
https://github.com/llvm/llvm-project/commit/a79186c1ea62bbe0579e0b1eed4ad507966cca41
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain.c
Log Message:
-----------
[Driver] Fix Arm/AArch64 Link Argument tests (#144582)
The openmp-offload-amdgpu-runtime-2 bot specifies default rtlib of
compiler-rt, but default unwindlib of libgcc. Change the tests to accept
that there may be `"--as-needed" "-lgcc_s" "--no-as-needed"` between
`libclang_rt.builtins.a` and `-lc`.
Relates to #121830
Commit: 7c4b2be983e900663a8d766ea9dc6f03b713e5b0
https://github.com/llvm/llvm-project/commit/7c4b2be983e900663a8d766ea9dc6f03b713e5b0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/streambuf
Log Message:
-----------
[libc++][NFC] Refactor basic_streambuf to use public API functions when possible (#144547)
The implementation of std::basic_streambuf used private member variables
to manipulate the get and the put areas. Using public API functions is
equivalent but leads to code that is easier to understand, since the
public API functions are known more widely than our internal member
variables. Using the public API functions removes the need to map the
internal member variables back to get/put area manipulation functions in
one's head.
Finally, it also makes it easier to find subtle issues by instrumenting
accessor functions, which is impossible if the class uses the member
variables directly.
Commit: 9ae4d2e01331ddeb2543f1940a09ef9c76ff5268
https://github.com/llvm/llvm-project/commit/9ae4d2e01331ddeb2543f1940a09ef9c76ff5268
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[LLVM] [Support] Disable `ioctl()` terminal size check on Solaris (#144600)
#143514 broke the `clang-solaris11-sparcv9` bot; from what I can tell
that’s Solaris and according to `SolarisTargetInfo::getOSDefines`, the
macro `__sun__` should be defined on Solaris, so check for that and
don’t try to query the terminal size if it is defined.
Not sure this is the best solution but hopefully it fixes the bot.
Commit: c677a11c8d3223480cfe772e63fa0e7c09c76e2e
https://github.com/llvm/llvm-project/commit/c677a11c8d3223480cfe772e63fa0e7c09c76e2e
Author: David Peixotto <peix at meta.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/source/Core/PluginManager.cpp
A lldb/test/API/commands/plugin/TestPlugin.py
M lldb/test/Shell/Commands/command-plugin-list.test
Log Message:
-----------
[lldb] Add support to list/enable/disable remaining plugin types. (#143970)
In #134418 we added support to list/enable/disable `SystemRuntime` and
`InstrumentationRuntime` plugins. We limited it to those two plugin
types to flesh out the idea with a smaller change.
This PR adds support for the remaining plugin types. We now support all
the plugins that can be registered directly with the plugin manager.
Plugins that are added by loading shared objects are still not
supported.
Commit: 908f74a25e01cc88d1dee1af5521d8fb1c21bc51
https://github.com/llvm/llvm-project/commit/908f74a25e01cc88d1dee1af5521d8fb1c21bc51
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/TargetMachine.h
Log Message:
-----------
[llvm] re-order LLVM_ABI and extern on NoKernelInfoEndLTO decl (#144601)
## Overview
Fix compilation error introduced by #143615. Build failure logs
available
[here](https://lab.llvm.org/buildbot/#/builders/195/builds/10573)
## Background
On `extern` variable declarations, `LLVM_ABI` must appear before
`extern` because `LLVM_ABI` currently resolves to
`[[gnu::visibility("default")]]` when building with gcc.
Commit: 49bf8d38d80ce43bd700f27833a7b8c8e7082af8
https://github.com/llvm/llvm-project/commit/49bf8d38d80ce43bd700f27833a7b8c8e7082af8
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
Log Message:
-----------
[gn build] Manually port b4e39e4f
Commit: 8d1610afd0db877460d1b3cd43cc4066478846a0
https://github.com/llvm/llvm-project/commit/8d1610afd0db877460d1b3cd43cc4066478846a0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
Log Message:
-----------
[libc++] Mark two assertion tests as unsupported in C++03 mode
Our assertion checking facility requires at least C++11, so these
tests were failing when run in C++03 mode.
Commit: 3c7df98c7b2a203e49a74b229bbf535c2ef6274b
https://github.com/llvm/llvm-project/commit/3c7df98c7b2a203e49a74b229bbf535c2ef6274b
Author: Piotr Idzik <65706193+vil02 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/performance/enum-size.rst
Log Message:
-----------
[clang-tidy] Add missing colon in the docs of performance-enum-size (#144525)
There is a syntax error in the provided code example - this PR fixes it.
I did a quick search - I could not find similar _typos_.
Commit: ecfb8fe5c1870091b095ae6ca1ad4cfc7158e619
https://github.com/llvm/llvm-project/commit/ecfb8fe5c1870091b095ae6ca1ad4cfc7158e619
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/aarch64-gnutools.c
R clang/test/Driver/aarch64-toolchain-extra.c
R clang/test/Driver/aarch64-toolchain.c
R clang/test/Driver/arm-gnutools.c
R clang/test/Driver/arm-toolchain-extra.c
R clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal-multilib.yaml
M clang/test/Driver/baremetal-sysroot.cpp
R clang/test/Driver/baremetal-undefined-symbols.c
M clang/test/Driver/baremetal.cpp
R clang/test/Driver/check-no-multlib-warning.c
A clang/test/Driver/riscv-args.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
Revert stack "[Driver] Add support for GCC installation detection in … (#144603)
…Baremetal toolchain (#121829)"
This reverts the following stack of commits, due to them breaking the
Fuchsia toolchain and corresponding LLVM buildbot.
Revert "[Driver] Fix Arm/AArch64 Link Argument tests (#144582)" This
reverts commit a79186c1ea62bbe0579e0b1eed4ad507966cca41.
Revert "[Driver] Add option to force undefined symbols during linking in
BareMetal toolchain object. (#132807)" This reverts commit
9cb754509608b9d9143fa17f775631bbfcce0848.
Revert "[Driver] Fix link order of BareMetal toolchain object (#132806)"
This reverts commit 31523de4b000ca254259ae3167d28922e1302648.
Revert "[Driver] Add support for crtbegin.o, crtend.o and libgloss lib
to BareMetal toolchain object (#121830)" This reverts commit
ec230aa7a7d13c222c0b34b87c3c16937383b4a0.
Revert "[Driver] Add support for GCC installation detection in Baremetal
toolchain (#121829)" This reverts commit
eb31c422d0dc816bf285a81bf92690d4d16273ed.
Commit: a5a0d880736f5dc6a566374bc3b3ca0d86901510
https://github.com/llvm/llvm-project/commit/a5a0d880736f5dc6a566374bc3b3ca0d86901510
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/__assert
M libcxx/src/verbose_abort.cpp
M libcxx/test/support/check_assertion.h
Log Message:
-----------
[libc++] Remove trailing newline from _LIBCPP_ASSERTION_HANDLER calls (#143573)
This newline was originally added in https://reviews.llvm.org/D142184
but I think updating `__libcpp_verbose_abort` to add newline instead is
more consistent, and works for other callers of `_LIBCPP_VERBOSE_ABORT`.
The `_LIBCPP_ASSERTION_HANDLER` calls through to either
`_LIBCPP_VERBOSE_ABORT` macro or the `__builtin_verbose_trap`. From what
I can tell neither of these function expect a trailing newline (at least
none of the usage of `_LIBCPP_VERBOSE_ABORT` or `__builtin_verbose_trap`
that I can find include a trailing newline except `_LIBCPP_ASSERTION_HANDLER`).
I noticed this discrepancy when working on
https://github.com/emscripten-core/emscripten/pull/24543
Commit: 844e41c2acedd5219d9363e38838abd5146f63c0
https://github.com/llvm/llvm-project/commit/844e41c2acedd5219d9363e38838abd5146f63c0
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libc/src/__support/wchar/character_converter.cpp
Log Message:
-----------
[libc] Moved shared constexpr to the top (#144569)
Some conversions shared constexpr so moved to the top.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 6fb36db4818abde56e5da47899dcdaacd8293903
https://github.com/llvm/llvm-project/commit/6fb36db4818abde56e5da47899dcdaacd8293903
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[LinkerWrapper] Fix 'save-temps' when targeting SPIR-V (#144605)
Summary:
The logic here is flawed, it was only intended to apply to the CPU case
where we use the linker passed in on the command line. This was falsely
applying to SPIR-V which caused issues.
Commit: 362b9d78b4ee9107da2b5e90b3764b0f0fa610fe
https://github.com/llvm/llvm-project/commit/362b9d78b4ee9107da2b5e90b3764b0f0fa610fe
Author: John Harrison <harjohn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/cancel/TestDAP_cancel.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
Log Message:
-----------
[lldb-dap] Refactoring DebugCommunication to improve test consistency. (#143818)
In DebugCommunication, we currently are using 2 thread to drive
lldb-dap. At the moment, they make an attempt at only synchronizing the
`recv_packets` between the reader thread and the main test thread. Other
stateful properties of the debug session are not guarded by a
locks/mutex.
To mitigate this, I am moving any state updates to the main thread
inside the `_recv_packet` method to ensure that between calls to
`_recv_packet` the state does not change out from under us in a test.
This does mean the precise timing of events has changed slightly as a
result and I've updated the existing tests that fail for me locally with
this new behavior.
I think this should result in overall more predictable behavior, even if
the test is slow due to the host workload or architecture differences.
---------
Co-authored-by: Ebuka Ezike <yerimyah1 at gmail.com>
Commit: 3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
https://github.com/llvm/llvm-project/commit/3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[clang] Add release note for int->enum conversion change. (#144407)
This seems to be having some practical impact, so we should let people
know.
Commit: f25f2f7de4f8264d89ba3c4dc9daddb10a90c13f
https://github.com/llvm/llvm-project/commit/f25f2f7de4f8264d89ba3c4dc9daddb10a90c13f
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Extend unrolling support for scatter ops with chunk_size (#144447)
Add support for load/store with chunk_size, which requires special
consideration for the operand blocking since offests and masks are
n-D and tensor are n+1-D. Support operations including create_tdesc,
update_tdesc, load, store, and prefetch.
---------
Co-authored-by: Adam Siemieniuk <adam.siemieniuk at intel.com>
Commit: fd7e46b864229a270726bd1026387740b9113094
https://github.com/llvm/llvm-project/commit/fd7e46b864229a270726bd1026387740b9113094
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/__assert
M libcxx/src/verbose_abort.cpp
M libcxx/test/support/check_assertion.h
Log Message:
-----------
Revert "[libc++] Remove trailing newline from _LIBCPP_ASSERTION_HANDLER calls" (#144615)
Reverts llvm/llvm-project#143573
Commit: 1cd18bc894b97b282677c1d140688a27ebbec924
https://github.com/llvm/llvm-project/commit/1cd18bc894b97b282677c1d140688a27ebbec924
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Add cost model tests for minimumnum/maximumnum (#141904)
The f16 cases in particular look broken since every vector size
has the same reported cost.
Commit: 87b13ada109643bbf5495727b0bf59a46bd533aa
https://github.com/llvm/llvm-project/commit/87b13ada109643bbf5495727b0bf59a46bd533aa
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/unittests/Frontend/HLSLRootSignatureDumpTest.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement serialization of remaining Root Elements (#143198)
Implements serialization of the remaining `RootElement`s, namely
`RootDescriptor`s and `StaticSampler`s.
- Adds unit testing for the serialization methods
Resolves https://github.com/llvm/llvm-project/issues/138191
Resolves https://github.com/llvm/llvm-project/issues/138193
Commit: cb63b75e32a415c9bfc298ed7fdcd67e8d9de54c
https://github.com/llvm/llvm-project/commit/cb63b75e32a415c9bfc298ed7fdcd67e8d9de54c
Author: John Harrison <harjohn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/cancel/TestDAP_cancel.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
Log Message:
-----------
Revert "[lldb-dap] Refactoring DebugCommunication to improve test consistency. (#143818)
This reverts commit 362b9d78b4ee9107da2b5e90b3764b0f0fa610fe.
Buildbots using python3.10 are running into errors from this change.
Commit: c9b28163888574bcfba0171372ae0dcfb40abbfa
https://github.com/llvm/llvm-project/commit/c9b28163888574bcfba0171372ae0dcfb40abbfa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
Log Message:
-----------
AMDGPU: Fix cost model for 16-bit operations on gfx8 (#141943)
We should only divide the number of pieces to fit the packed instructions
if we actually have pk instructions. This increases the cost of copysign,
but is closer to the current codegen output. It could be much cheaper
than it is now.
Commit: 3800a83160a42f32947b82700e454cc07c600734
https://github.com/llvm/llvm-project/commit/3800a83160a42f32947b82700e454cc07c600734
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
Log Message:
-----------
AMDGPU: Reduce cost of f64 copysign (#141944)
The real implementation is 1 real instruction plus a constant
materialize. Call that a 1, it's not a real f64 operation.
Commit: bec9ac2dafe1c9fca975721e9951c5f7f6b1b559
https://github.com/llvm/llvm-project/commit/bec9ac2dafe1c9fca975721e9951c5f7f6b1b559
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
Log Message:
-----------
[llvm] Lower latency bonus threshold in function specialization. (#143954)
Related to #143219.
Function specialization does not kick in if flang sets `noalias`
attributes on the function arguments of `digits_2`, because PRE
optimizes several `srem` instructions and other memory accesses
from the inner loops causing the latency bonus to be lower than
the current 40% threshold.
While looking at this, I did not really get why we compute the latency
bonus as a ratio of the latency of the "eliminated" instructions
and the code-size of the whole function. It did not make much sense
to me.
I tried computing the total latency as a sum of latencies
of the instructions that belong to non-dead code (including
the instructions that would be executed had they not been
"eliminated" due to the constant propagation). This total
latency should identify the total cost of executing the function
with the given argument being dynamically equal to the tried
constant value. Then the latency bonus would be computed
as the ratio between the latency of the "eliminated" instructions
and the total latency. Unfortunately, this did not given me a good
heuristics either. The bonus was close to 0% on some targets,
and as big as 3-5% on other targets. This does match very well
with the performance gain achieved by function specialization
for exchange2, so it seemd like another artificial heuristic
not better than the current one.
It seems that GCC uses a set of different heuristics for function
specialization, but I am not an expert here and I cannot say
if we can match them in LLVM.
With all that said, I decided to try to lower the threshold
to avoid the regression and be able to re-enable the generally
good change for `noalias` attribute.
With this patch, I was able to reduce the effect of `noalias`,
so that `-force-no-alias=true` is only ~10% slower than
`-force-no-alias=false` code on neoverse-v1 and neoverse-v2.
On neoverse-n1, `-force-no-alias=true` is >2x faster than
`-force-no-alias=false` regardless of this patch.
This threshold has been changed before also due to improved
alias information:
https://github.com/llvm/llvm-project/commit/2fb51fba8ca904a6d3ddf30ae94228ecf9e6a231#diff-066363256b7b4164e66b28a3028b2cb9e405c9136241baa33db76ebd2edb87cd
Please let me know what testing I should run to make sure this change
is safe. As I understand, it may affect the compilation time
performance,
and I will appreciate it if someone points out which benchmarks
need to be checked before merging this.
Commit: af65cb68f553759eac307edda87ff7d8b5fdffa9
https://github.com/llvm/llvm-project/commit/af65cb68f553759eac307edda87ff7d8b5fdffa9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
Log Message:
-----------
AMDGPU: Move fpenvIEEEMode into TTI (#141945)
Commit: 70343c8d44273c187e3f7fa5e2037fbc41307077
https://github.com/llvm/llvm-project/commit/70343c8d44273c187e3f7fa5e2037fbc41307077
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
A flang/test/Fir/cfg-conversion-if.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][flang] Added Weighted[Region]BranchOpInterface's. (#142079)
The new interfaces provide getters and setters for the weight
information about the branches of BranchOpInterface and
RegionBranchOpInterface operations.
These interfaces are done the same way as LLVM dialect's
BranchWeightOpInterface.
The plan is to produce this information in Flang, e.g. mark
most probably "cold" code as such and allow LLVM to order
basic blocks accordingly. An example of such a code is
copy loops generated for arrays repacking - we can mark it
as "cold" assuming that the copy will not happen dynamically.
If the copy actually happens the overhead of the copy is probably high
enough so that we may not care about the little overhead
of jumping to the "cold" code and fetching it.
Commit: 54015f36c682aab9024a21a93957312a69c5bc9b
https://github.com/llvm/llvm-project/commit/54015f36c682aab9024a21a93957312a69c5bc9b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
Log Message:
-----------
AMDGPU: Cost model for minimumnum/maximumnum (#141946)
Commit: f08474ab1fa984560565e917453a42bc8562a6f9
https://github.com/llvm/llvm-project/commit/f08474ab1fa984560565e917453a42bc8562a6f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
Log Message:
-----------
AMDGPU: Add baseline cost model tests for special argument intrinsics (#141947)
Commit: f3af1cd08cd456214961af915c17f858c9eef1a5
https://github.com/llvm/llvm-project/commit/f3af1cd08cd456214961af915c17f858c9eef1a5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
Log Message:
-----------
[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. (#144571)
We know that vlenb is a multiple of RVVBytesPerBlock so we aren't
shifting out any non-zero bits.
Commit: a9811340b75baae8e06fb9ab83015a90d61510ee
https://github.com/llvm/llvm-project/commit/a9811340b75baae8e06fb9ab83015a90d61510ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
Log Message:
-----------
AMDGPU: Report special input intrinsics as free (#141948)
Commit: 628274dadf92995f4544d6134cba45d327d9eaaa
https://github.com/llvm/llvm-project/commit/628274dadf92995f4544d6134cba45d327d9eaaa
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A llvm/include/llvm/DebugInfo/DWARF/DWARFCFIPrinter.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFCFIProgram.h
M llvm/lib/DebugInfo/DWARF/CMakeLists.txt
A llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIProgram.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
Log Message:
-----------
[NFC] Extract Printing portions of DWARFCFIProgram to new files (#143762)
CFIPrograms' most common uses are within debug frames, but it is not
their only use. For example, some assembly writers encode them by hand
into .cfi_escape directives. This PR extracts printing code for them
into its own files, which avoids the need for the main class to depend
on DWARFUnit, sections, and similar.
One in a series of NFC DebugInfo/DWARF refactoring changes to layer it
more cleanly, so that binary CFI parsing can be used from low-level
code, (such as byte strings created via .cfi_escape) without circular
dependencies. The final goal is to make a more limited dwarf library
usable from lower-level code.
More information can be found at
https://discourse.llvm.org/t/rfc-debuginfo-dwarf-refactor-into-to-lower-and-higher-level-libraries/86665
Commit: a871b919ed135b3b50db58ed816d6ddb488d9c5e
https://github.com/llvm/llvm-project/commit/a871b919ed135b3b50db58ed816d6ddb488d9c5e
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 9e0186d925f0
Commit: 535291409cc7e4ae571318a38bd3617d7f608002
https://github.com/llvm/llvm-project/commit/535291409cc7e4ae571318a38bd3617d7f608002
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
Log Message:
-----------
[gn build] Port 9ec75a50bc48
Commit: 6652961ae5fee4d81871e4310a9e842c61136c10
https://github.com/llvm/llvm-project/commit/6652961ae5fee4d81871e4310a9e842c61136c10
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn build] Manually port 556e69b7
Commit: b164d3613ad9b86a8b951cfc43fadc0edfc7644e
https://github.com/llvm/llvm-project/commit/b164d3613ad9b86a8b951cfc43fadc0edfc7644e
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 628274dadf92
Commit: f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
https://github.com/llvm/llvm-project/commit/f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/builtin-is-constant-evaluated.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/cxx0x-class.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaTemplate/instantiate-static-var.cpp
Log Message:
-----------
[clang] Remove separate evaluation step for static class member init. (#142713)
We already evaluate the initializers for all global variables, as
required by the standard. Leverage that evaluation instead of trying to
separately validate static class members.
This has a few benefits:
- Improved diagnostics; we now get notes explaining what failed to
evaluate.
- Improved correctness: is_constant_evaluated is handled correctly.
The behavior follows the proposed resolution for CWG1721.
Fixes #88462. Fixes #99680.
Commit: c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
https://github.com/llvm/llvm-project/commit/c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/MC/Disassembler/Xtensa/coprocessor.txt
A llvm/test/MC/Disassembler/Xtensa/debug.txt
A llvm/test/MC/Disassembler/Xtensa/exception.txt
A llvm/test/MC/Disassembler/Xtensa/highinterrupts.txt
A llvm/test/MC/Disassembler/Xtensa/interrupt.txt
A llvm/test/MC/Disassembler/Xtensa/prid.txt
A llvm/test/MC/Disassembler/Xtensa/timer.txt
M llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/coprocessor.s
A llvm/test/MC/Xtensa/debug-invalid.s
A llvm/test/MC/Xtensa/debug.s
A llvm/test/MC/Xtensa/exception.s
A llvm/test/MC/Xtensa/highinterrupts.s
A llvm/test/MC/Xtensa/interrupt.s
A llvm/test/MC/Xtensa/prid.s
A llvm/test/MC/Xtensa/timer.s
Log Message:
-----------
[Xtensa] Implement Xtensa Interrupt/Exception/Debug Options. (#143820)
Implement Xtensa Interrupt. HighInterrupts, Exception, Debug Options.
Also implement small Xtensa Options like PRID, Coprocessor and Timers.
Commit: 15482c83aa2b05779d7ad947c34835656ab9da1c
https://github.com/llvm/llvm-project/commit/15482c83aa2b05779d7ad947c34835656ab9da1c
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
A llvm/test/Transforms/EliminateAvailableExternally/convert-global-variables-to-local.ll
Log Message:
-----------
[ElimAvailExtern] Add an option to allow to convert global variables in a specified address space to local (#144287)
Currently, the `EliminateAvailableExternallyPass` only converts certain
available externally functions to local if `avail-extern-to-local` is
set or in
contextual profiling mode. For global variables, it only drops their
initializers.
This PR adds an option to allow the pass to convert global variables in
a
specified address space to local. The motivation for this change is to
correctly
support lowering of LDS variables (`__shared__` variables, in more
generic
terminology) when ThinLTO is enabled for AMDGPU.
A `__shared__` variable is lowered to a hidden global variable in a
particular
address space by the frontend, which is roughly same as a `static` local
variable. To properly lower it in the backend, the compiler needs to
check all
its uses. Enabling ThinLTO currently breaks this when a function
containing a
`__shared__` variable is imported from another module. Even though the
global
variable is imported along with its associated function, and the
function is
privatized by the `EliminateAvailableExternallyPass`, the global
variable itself
is not.
It's safe to privatize such global variables, because they're _local_ to
their
associated functions. If the function itself is privatized, its
associated
global variables should also be privatized accordingly.
Commit: 64155a32297f4884875783664ff13bec9ab376f5
https://github.com/llvm/llvm-project/commit/64155a32297f4884875783664ff13bec9ab376f5
Author: Minding <77574923+Minding000 at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm-c/ExecutionEngine.h
Log Message:
-----------
Added clarifying comment to 'LLVMLinkInMCJIT' and 'LLVMLinkInInterpreter' (#92467)
Clarify that these functions are no-ops when linking to LLVM as a shared object.
Commit: abbdd1670d8b12dd72ec353b14e256619ff4694b
https://github.com/llvm/llvm-project/commit/abbdd1670d8b12dd72ec353b14e256619ff4694b
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/Object/ELF.h
M llvm/lib/BinaryFormat/Dwarf.cpp
Log Message:
-----------
[llvm] minor fixes for clang-cl Windows DLL build (#144386)
## Purpose
This patch makes a minor changes to LLVM and Clang so that LLVM can be
built as a Windows DLL with `clang-cl`. These changes were not required
for building a Windows DLL with MSVC.
## Background
The Windows DLL effort is tracked in #109483. Additional context is
provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
## Overview
Specific changes made in this patch:
- Remove `constexpr` fields that reference DLL exported symbols. These
symbols cannot be resolved at compile time when building a Windows DLL
using `clang-cl`, so they cannot be `constexpr`. Instead, they are made
`const` and initialized in the implementation file rather than at
declaration in the header.
- Annotate symbols now defined out-of-line with `LLVM_ABI` so they are
exported when building as a shared library.
- Explicitly add default copy assignment operator for `ELFFile` to
resolve a compiler warning.
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
Commit: 99e263228f4513c166f20469968b2b646edaaa33
https://github.com/llvm/llvm-project/commit/99e263228f4513c166f20469968b2b646edaaa33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
github: Add mips backend to PR autolabeler (#140909)
Commit: 4e090b6e84e33e2a442e3951253ca570f8f842f8
https://github.com/llvm/llvm-project/commit/4e090b6e84e33e2a442e3951253ca570f8f842f8
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Core/DynamicLoader.cpp
Log Message:
-----------
[lldb] Re-insert code to search for a binary by filepath if provided
July 14 2024 I landed a change to update progress reporting when
loading kernel/firmware binaries
https://github.com/llvm/llvm-project/pull/98845
In DynamicLoader::LoadBinaryWithUUIDAndAddress I removed code that
was setting the ModuleSpec to the provided name, if the name provided
is that of a file on disk. With this code missing, if a filepath
name is passed in, this code will fail to find that binary on the local
disk. There's nothing in the PR / intention that would lead to this
change, it was unintentional.
Commit: 86a09f36154fbd264f61ea6462c8cf48b1ff2eb0
https://github.com/llvm/llvm-project/commit/86a09f36154fbd264f61ea6462c8cf48b1ff2eb0
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[MLIR][XeGPU] Clean up xegpu op tests (#144592)
Test cleanup:
1) separate layout.mlir from ops.mlir for layout related test
2) remove lane layout for ops working at work item scope.
3) remove redundant test in create_tdesc/update_tdesc/prefetch.
4) remove "test_" from all test function name.
Commit: 0defde8e06338cbe968d55d1d9e8581d55f3ae2b
https://github.com/llvm/llvm-project/commit/0defde8e06338cbe968d55d1d9e8581d55f3ae2b
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
Log Message:
-----------
[AMDGPU] Support D16 folding for image.sample with multiple extractelement and fptrunc users (#141758)
Now we only support D16 folding for `image sample` instructions with a
single user: a `fptrunc` to half.
However, we can actually support D16 folding for image.sample
instructions with multiple users,
as long as each user follows the pattern of extractelement followed by
fptrunc to half.
For example:
```
%sample = call <4 x float> @llvm.amdgcn.image.sample
%e0 = extractelement <4 x float> %sample, i32 0
%h0 = fptrunc float %e0 to half
%e1 = extractelement <4 x float> %sample, i32 1
%h1 = fptrunc float %e1 to half
%e2 = extractelement <4 x float> %sample, i32 2
%h2 = fptrunc float %e2 to half
```
This change enables D16 folding for such cases and avoids generating
`v_cvt_f16_f32_e32` instructions.
Commit: 9265b1f0cff74c929214efb64f41183299f31772
https://github.com/llvm/llvm-project/commit/9265b1f0cff74c929214efb64f41183299f31772
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/test/Transforms/LowerTypeTests/blockaddress-2.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/LowerTypeTests/function-disjoint.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/icall-branch-funnel.ll
M llvm/test/Transforms/LowerTypeTests/pr37625.ll
M llvm/test/Transforms/LowerTypeTests/section.ll
Log Message:
-----------
LowerTypeTests: Use jump table entry type as value type of jump table alias.
The motivation for this is that it causes the jump table entry's symbol
to have an st_size equal to the jump table entry size, instead of being
equal to the size of the entire jump table, which is incorrect and can
lead to unexpected behavior in binary analysis tools that rely on the
size field such as Bloaty.
Reviewers: fmayer
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/144462
Commit: 8ddada41df0488358373cff1d31a47e5ef4961e0
https://github.com/llvm/llvm-project/commit/8ddada41df0488358373cff1d31a47e5ef4961e0
Author: Jim Lin <jim at andestech.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features-andes.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/xandesvbfhcvt-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
Commit: a96a3f1b26baa8e5ee0abbac629f02566b7e9d1c
https://github.com/llvm/llvm-project/commit/a96a3f1b26baa8e5ee0abbac629f02566b7e9d1c
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
Log Message:
-----------
[lldb][Minidump Parser] Implement a range data vector for minidump memory ranges (#136040)
Recently I was debugging a Minidump with a few thousand ranges, and came
across the (now deleted) comment:
```
// I don't have a sense of how frequently this is called or how many memory
// ranges a Minidump typically has, so I'm not sure if searching for the
// appropriate range linearly each time is stupid. Perhaps we should build
// an index for faster lookups.
```
blaming this comment, it's 9 years old! Much overdue for this simple fix
with a range data vector.
I had to add a default constructor to Range in order to implement the
RangeDataVector, but otherwise this just a replacement of look up logic.
Commit: a2ad65661ad560b04952d4d992248d2db3be36c8
https://github.com/llvm/llvm-project/commit/a2ad65661ad560b04952d4d992248d2db3be36c8
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcibm-cto-clo.ll
Log Message:
-----------
[RISCV] Add patterns for generating QC_CTO and QC_CLO (#144532)
These instructions count leading/trailing ones in the register.
Currently these are only generated when we have `Zbb` enabled (along
with `Xqcibm`) since it contains the `CTTZ/CTLZ` instructions.
Commit: e14f327d8094e02134efa98625acaf6fd43fee08
https://github.com/llvm/llvm-project/commit/e14f327d8094e02134efa98625acaf6fd43fee08
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
Log Message:
-----------
[RISCV] Pre-test for #144461
Commit: af49a650e172d56d684581b66afa9ab0368ec8f9
https://github.com/llvm/llvm-project/commit/af49a650e172d56d684581b66afa9ab0368ec8f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Add baseline tests for more f128 libcall handling (#144381)
Some of these incorrectly call the l suffixed version of libm
functions and others assert.
Commit: 7b9d10d2e6410029fd0750b2e0566432dbf03dc7
https://github.com/llvm/llvm-project/commit/7b9d10d2e6410029fd0750b2e0566432dbf03dc7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Fix using long double libm functions for f128 intrinsics (#144382)
This wasn't setting the correct libcall names, which default to the
l suffixed libm names.
Commit: ad9e591fd53f2cf91a2744973b59669d873658af
https://github.com/llvm/llvm-project/commit/ad9e591fd53f2cf91a2744973b59669d873658af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[SelectionDAG][RISCV] Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)) in getNode. (#144565)
We already have shl/mul vscale related folds in getNode.
This is an alternative to the DAGCombine proposed in #144507.
Commit: 74687180dde07312521db09c6f6454fe9d1e5662
https://github.com/llvm/llvm-project/commit/74687180dde07312521db09c6f6454fe9d1e5662
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc] Make CExpression trait into interface (#142771)
By defining `CExpressionInterface`, we move the side effect detection
logic from `emitc.expression` into the individual operations
implementing the interface allowing operations to gradually tune the
side effect.
It also allows checking for side effects each operation individually.
Commit: 10f29a607205c0c17ee9249a66feb63f0fdae182
https://github.com/llvm/llvm-project/commit/10f29a607205c0c17ee9249a66feb63f0fdae182
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/msan/msan_interceptors.cpp
Log Message:
-----------
[MSan] Fix wrong unpoison size in SignalAction (#144071)
MSan should unpoison the parameters of extended signal handlers.
However, MSan unpoisoned the second parameter with the wrong size
`sizeof(__sanitizer_sigaction)`, inconsistent with its real type
`siginfo_t`.
This commit fixes this issue by correcting the size to
`sizeof(__sanitizer_siginfo)`.
Commit: 4d71f20b287e398f10bbff55d52bec9683ef89d2
https://github.com/llvm/llvm-project/commit/4d71f20b287e398f10bbff55d52bec9683ef89d2
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#133335)
This commit prevents building a G_UNMERGE_VALUES instruction with
different source and destination vector elements in
`LegalizationArtifactCombiner::ArtifactValueFinder::tryCombineMergeLike()`,
e.g.:
`%1:_(<2 x s8>), %2:_(<2 x s8>) = G_UNMERGE_VALUES %0:_(<2 x s16>)`
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 896e187a6e923b8441428f9db63c412d989fc51d
https://github.com/llvm/llvm-project/commit/896e187a6e923b8441428f9db63c412d989fc51d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndMaskToShift - pull out repeated SDLoc(). NFC.
Commit: dac94f28e696e8234ec69bbed549533ea6b00227
https://github.com/llvm/llvm-project/commit/dac94f28e696e8234ec69bbed549533ea6b00227
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotOrIntoAndNotAnd - pull out repeated SDLoc(). NFC.
Commit: 0875bee2b10185eca40aea3b3f49eb8462522eda
https://github.com/llvm/llvm-project/commit/0875bee2b10185eca40aea3b3f49eb8462522eda
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotIntoANDNP - pull out repeated SDLoc(). NFC.
Commit: 44b715293fcad79ef4a54474627ac574a759fa5a
https://github.com/llvm/llvm-project/commit/44b715293fcad79ef4a54474627ac574a759fa5a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Copy FMUL+ADDSUB/FMADDSUB build vector patterns from codegen tests
As detailed on #144489 - confirm the vectorisation of scalar FMUL+ADDSUB/FMADDSUB on various targets
Commit: 45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
https://github.com/llvm/llvm-project/commit/45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/aarch64-gnutools.c
A clang/test/Driver/aarch64-toolchain-extra.c
A clang/test/Driver/aarch64-toolchain.c
A clang/test/Driver/arm-gnutools.c
A clang/test/Driver/arm-toolchain-extra.c
A clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
A clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
Reland [Driver] Add support for GCC installation detection in Baremetal toolchain (#144640)
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is derived from those locations.
- If not, the logic falls back to the existing sysroot inference
mechanism already present in the Baremetal toolchain.
- Support for adding include paths for the libstdc++ library has also
been added.
Additionally, the restriction to always use the integrated assembler has
been removed. With a valid GCC installation, the GNU assembler can now
be used as well.
This patch currently updates and adds tests for the ARM target only.
RISC-V-specific tests will be introduced in a later patch, once the
RISCVToolChain is fully merged into the Baremetal toolchain. At this
stage, there is no way to test the RISC-V target within this PR.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: e07b1b26c38ba48af247b370a29eeb9879cefc97
https://github.com/llvm/llvm-project/commit/e07b1b26c38ba48af247b370a29eeb9879cefc97
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] Implement SDPatternMatch `m_Abs()` matcher (#144512)
Commit: a38932ac3c0a16226e3dde7f1532f117959c58df
https://github.com/llvm/llvm-project/commit/a38932ac3c0a16226e3dde7f1532f117959c58df
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
Revert "[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements" (#144650)
Reverts llvm/llvm-project#133335
Commit: 49df87e71b73b230ecb21335dcb5f5390eebdab3
https://github.com/llvm/llvm-project/commit/49df87e71b73b230ecb21335dcb5f5390eebdab3
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc][printf] Fix out-of-range shift in float320 printf (#144542)
If you enable `LIBC_CONF_PRINTF_FLOAT_TO_STR_USE_FLOAT320` and use a
`%f` style printf format directive to print a nonzero number too small
to show up in the output digits, e.g. `printf("%.2f", 0.001)`, then the
output would be intermittently incorrect, because
`DyadicFloat::as_mantissa_type_rounded` would try to shift the 320-bit
mantissa right by more than 320 bits, invoking the 'undefined behavior'
clause commented in the `shift()` function in `big_int.h`.
There were already tests in the libc test suite exercising this case,
e.g. the subnormal tests in `LlvmLibcSPrintfTest.FloatDecimalConv` use
`%f` at the default precision of 6 decimal places on tiny numbers such
as 2^-1027. But because the behavior is undefined, they don't visibly
fail all the time, and in all previous test runs we'd tried with
USE_FLOAT320, they had got lucky.
The fix is simply to detect an out-of-range right shift before doing it,
and instead just set the output value to zero.
Commit: ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
https://github.com/llvm/llvm-project/commit/ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
Log Message:
-----------
[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772)
When the fixed-order recurrence phi is live-out from the loop, the
vectorizer uses VPInstruction::ExtractPenultimateElement to extract the
penultimate element from the recurrence vector. However, this is not
feasible when the VF is vscale x 1, since vscale could be 1, making the
vector contain only one element.
This patch changes the behavior for vscale x 1 by extracting the last
element from the vector produced by splicing the recurrence phi and the
previous value. This ensures we can still determine the correct live-out
value of the recurrence phi.
Commit: aba71acc80b73b134d141449db6abc7620187a59
https://github.com/llvm/llvm-project/commit/aba71acc80b73b134d141449db6abc7620187a59
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M .github/new-prs-labeler.yml
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/callcont-fallthru.s
M bolt/test/lit.local.cfg
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.cpp
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.h
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
A clang-tools-extra/clangd/test/positionencoding.test
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/enum-size.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-value-param.rst
A clang-tools-extra/test/clang-tidy/checkers/performance/unnecessary-value-param-coroutine.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/Toolchain.rst
M clang/docs/UsersManual.rst
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Scope.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/InterpBlock.cpp
M clang/lib/AST/ByteCode/InterpStack.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/__clang_cuda_intrinsics.h
A clang/lib/Headers/cuda_wrappers/bits/c++config.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/DivZeroChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/test/Analysis/NewDelete-checker-test.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bugfix-124477.m
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/taint-generic.c
M clang/test/CIR/CodeGen/string-literals.c
A clang/test/CIR/CodeGen/string-literals.cpp
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/aarch64-gnutools.c
A clang/test/Driver/aarch64-toolchain-extra.c
A clang/test/Driver/aarch64-toolchain.c
A clang/test/Driver/arm-gnutools.c
A clang/test/Driver/arm-toolchain-extra.c
A clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
A clang/test/Driver/check-no-multlib-warning.c
M clang/test/Driver/fveclib.c
A clang/test/Driver/ignored-pch.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
A clang/test/Modules/preferred_name_header_unit.cpp
A clang/test/PCH/Inputs/ignored-pch.h
A clang/test/PCH/ignored-pch.c
M clang/test/Preprocessor/riscv-target-features-andes.c
A clang/test/Sema/gh87867.c
M clang/test/SemaCXX/builtin-is-constant-evaluated.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/cxx0x-class.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaTemplate/instantiate-static-var.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/lsan/lsan_allocator.cpp
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Support/OpenMP-features.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Driver/flang-openmp-version-macro.f90
A flang/test/Fir/cfg-conversion-if.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
A flang/test/Lower/OpenMP/Todo/omp-clause-indirect.f90
R flang/test/Lower/OpenMP/Todo/target-parallel-private.f90
R flang/test/Lower/OpenMP/Todo/target-teams-private.f90
A flang/test/Lower/OpenMP/copyprivate5.f90
A flang/test/Lower/OpenMP/target-parallel-private.f90
A flang/test/Lower/OpenMP/target-teams-private.f90
A flang/test/Parser/OpenMP/declare-target-indirect-tree.f90
M flang/test/Semantics/OpenMP/parallel-sections01.f90
A flang/test/Semantics/OpenMP/sections-goto.f90
M flang/test/Semantics/OpenMP/sections02.f90
A flang/test/Semantics/indirect01.f90
A flang/test/Semantics/indirect02.f90
M flang/test/Semantics/modfile75.F90
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/wchar/character_converter.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/wchar/CMakeLists.txt
A libc/test/src/__support/wchar/utf8_to_32_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/rename_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/strtold_test.cpp
M libcxx/include/fstream
M libcxx/include/streambuf
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
M lld/MachO/DriverUtils.cpp
M lld/test/ELF/lto/aarch64-pac-got-func.ll
A lld/test/MachO/reexport-with-symlink.s
M lldb/cmake/modules/FindPythonAndSwig.cmake
M lldb/include/lldb/Core/PluginManager.h
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.cpp
M lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.h
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.cpp
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.h
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
A lldb/test/API/commands/plugin/TestPlugin.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string/TestDataFormatterLibcxxString.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/string_view/TestDataFormatterLibcxxStringView.py
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/API/tools/lldb-dap/save-core/TestDAP_save_core.py
M lldb/test/Shell/Commands/command-plugin-list.test
A lldb/test/Shell/ObjectFile/XCOFF/symbol-info.yaml
A lldb/test/Shell/ObjectFile/XCOFF/symbol-info32.yaml
M lldb/test/Shell/lit.cfg.py
M llvm/cmake/config-ix.cmake
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/ExecutionEngine.h
M llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/Config/config.h.cmake
A llvm/include/llvm/DebugInfo/DWARF/DWARFCFIPrinter.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFCFIProgram.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCExpr.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Option/OptSpecifier.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/Transforms/IPO.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/include/llvm/Transforms/Utils/PromoteMemToReg.h
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/CallGraph.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/DemandedBits.cpp
M llvm/lib/Analysis/IR2Vec.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/DebugInfo/DWARF/CMakeLists.txt
A llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIProgram.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Support/Unix/Process.inc
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
M llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
M llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
M llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
M llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
R llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/MipsTargetObjectFile.cpp
M llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
R llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp
M llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
M llvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
M llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
M llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
M llvm/lib/Target/XCore/XCoreAsmPrinter.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/ADCE.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Evaluator.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
A llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-libmvec-scalable.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-libmvec.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-sdiv-pow2.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/noop_bitcast_global_array_type.ll
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/bug26185.ll
M llvm/test/CodeGen/NVPTX/i1-ext-load.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
A llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
A llvm/test/CodeGen/RISCV/xqcibm-cto-clo.ll
A llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
M llvm/test/CodeGen/X86/horizontal-sum.ll
A llvm/test/MC/Disassembler/Xtensa/coprocessor.txt
A llvm/test/MC/Disassembler/Xtensa/debug.txt
A llvm/test/MC/Disassembler/Xtensa/exception.txt
A llvm/test/MC/Disassembler/Xtensa/highinterrupts.txt
A llvm/test/MC/Disassembler/Xtensa/interrupt.txt
A llvm/test/MC/Disassembler/Xtensa/prid.txt
A llvm/test/MC/Disassembler/Xtensa/timer.txt
A llvm/test/MC/RISCV/xandesvbfhcvt-valid.s
M llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/coprocessor.s
A llvm/test/MC/Xtensa/debug-invalid.s
A llvm/test/MC/Xtensa/debug.s
A llvm/test/MC/Xtensa/exception.s
A llvm/test/MC/Xtensa/highinterrupts.s
A llvm/test/MC/Xtensa/interrupt.s
A llvm/test/MC/Xtensa/prid.s
A llvm/test/MC/Xtensa/timer.s
M llvm/test/Transforms/DeadStoreElimination/trivial-dse-calls.ll
A llvm/test/Transforms/EliminateAvailableExternally/convert-global-variables-to-local.ll
M llvm/test/Transforms/GVN/opt-remarks.ll
M llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstSimplify/ConstProp/loads.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-minmax.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LowerTypeTests/blockaddress-2.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/LowerTypeTests/function-disjoint.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/icall-branch-funnel.ll
M llvm/test/Transforms/LowerTypeTests/pr37625.ll
M llvm/test/Transforms/LowerTypeTests/section.ll
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/isCommutative.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Frontend/CMakeLists.txt
M llvm/unittests/Frontend/HLSLRootSignatureDumpTest.cpp
A llvm/unittests/Frontend/HLSLRootSignatureRangesTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/LoongArch/CMakeLists.txt
M llvm/unittests/Target/RISCV/CMakeLists.txt
M llvm/unittests/Target/SPIRV/CMakeLists.txt
M llvm/unittests/Target/VE/CMakeLists.txt
M llvm/unittests/Target/WebAssembly/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
M mlir/docs/Dialects/Vector.md
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Query/Matcher/MatchFinder.h
M mlir/include/mlir/Query/Matcher/MatchersInternal.h
M mlir/include/mlir/Query/Matcher/SliceMatchers.h
M mlir/include/mlir/Query/Matcher/VariantValue.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Query/Matcher/CMakeLists.txt
A mlir/lib/Query/Matcher/MatchersInternal.cpp
M mlir/lib/Query/Matcher/RegistryManager.cpp
M mlir/lib/Query/Matcher/VariantValue.cpp
M mlir/lib/Query/Query.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/CMakeLists.txt
M mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir
A mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
A mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir
A mlir/test/Target/LLVMIR/openmp-task-charbox.mlir
M mlir/test/Target/SPIRV/constant.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lit.cfg.py
A mlir/test/lit.local.cfg
M mlir/test/lit.site.cfg.py.in
A mlir/test/mlir-query/backward-slice-union.mlir
R mlir/test/mlir-query/complex-test.mlir
A mlir/test/mlir-query/forward-slice-by-predicate.mlir
A mlir/test/mlir-query/logical-operator-test.mlir
A mlir/test/mlir-query/slice-function-extraction.mlir
M mlir/tools/mlir-query/mlir-query.cpp
M mlir/utils/vscode/package-lock.json
M mlir/utils/vscode/package.json
A offload/cmake/caches/AMDGPULibcBot.cmake
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/config.bzl
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
M utils/bazel/llvm_configs/config.h.cmake
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/3486f727b992...aba71acc80b7
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