[all-commits] [llvm/llvm-project] ad9e59: [SelectionDAG][RISCV] Fold (add (vscale * C0), (vs...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad9e591fd53f2cf91a2744973b59669d873658af
      https://github.com/llvm/llvm-project/commit/ad9e591fd53f2cf91a2744973b59669d873658af
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-17 (Tue, 17 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)) in getNode. (#144565)

We already have shl/mul vscale related folds in getNode.

This is an alternative to the DAGCombine proposed in #144507.



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