[all-commits] [llvm/llvm-project] c21a4c: [Xtensa] Implement Xtensa Interrupt/Exception/Debu...

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
      https://github.com/llvm/llvm-project/commit/c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2025-06-18 (Wed, 18 Jun 2025)

  Changed paths:
    M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
    M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
    M llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    A llvm/test/MC/Disassembler/Xtensa/coprocessor.txt
    A llvm/test/MC/Disassembler/Xtensa/debug.txt
    A llvm/test/MC/Disassembler/Xtensa/exception.txt
    A llvm/test/MC/Disassembler/Xtensa/highinterrupts.txt
    A llvm/test/MC/Disassembler/Xtensa/interrupt.txt
    A llvm/test/MC/Disassembler/Xtensa/prid.txt
    A llvm/test/MC/Disassembler/Xtensa/timer.txt
    M llvm/test/MC/Xtensa/Core/processor-control.s
    A llvm/test/MC/Xtensa/coprocessor.s
    A llvm/test/MC/Xtensa/debug-invalid.s
    A llvm/test/MC/Xtensa/debug.s
    A llvm/test/MC/Xtensa/exception.s
    A llvm/test/MC/Xtensa/highinterrupts.s
    A llvm/test/MC/Xtensa/interrupt.s
    A llvm/test/MC/Xtensa/prid.s
    A llvm/test/MC/Xtensa/timer.s

  Log Message:
  -----------
  [Xtensa] Implement Xtensa Interrupt/Exception/Debug Options. (#143820)

Implement Xtensa Interrupt. HighInterrupts, Exception, Debug Options.
Also implement small Xtensa Options like PRID, Coprocessor and Timers.



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