[all-commits] [llvm/llvm-project] f3af1c: [RISCV] Set the exact flag on the SRL created for ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3af1cd08cd456214961af915c17f858c9eef1a5
      https://github.com/llvm/llvm-project/commit/f3af1cd08cd456214961af915c17f858c9eef1a5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-17 (Tue, 17 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

  Log Message:
  -----------
  [RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. (#144571)

We know that vlenb is a multiple of RVVBytesPerBlock so we aren't
shifting out any non-zero bits.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications