[all-commits] [llvm/llvm-project] ef9547: [RISCV] Fold (add (srl x, n), (srl x, n)) into (sr...

[Björn Pettersson via All-commits]

  Branch: refs/heads/users/bjope/prepare_1
  Home:   https://github.com/llvm/llvm-project
  Commit: ef9547df04cbf0eb7e756a790f90a64704b57975
      https://github.com/llvm/llvm-project/commit/ef9547df04cbf0eb7e756a790f90a64704b57975
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-17 (Tue, 17 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [RISCV] Fold (add (srl x, n), (srl x, n)) into (srl x, n-1)

This patch adds a new fold that will turn
  (add (srl x, n), (srl x, n))
into
  (srl x, n-1)
when bit n-1 is known to be zero in x.

This could perhaps be moved to generic DAGCombiner in the
future, but this patch adds it as a RISCV specific combine.
For RISCV it typically trigger for DAG nodes like this that
may be created by the legalizer:
  t1: i32 = srl RISCVISD::READ_VLENB:i32, Constant:i32<2>
  t2: i32 = add t1, t1

Got the idea when working on a solution for #141034, as it
may avoid some regressions otherwise caused by the fix being
prepared for that issue.



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