[all-commits] [llvm/llvm-project] a733c6: [TargetLowering][RISCV] Allow scalable non-simple ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a733c6c7bb1c533ec28c96c49d3c5de7babd8b7f
      https://github.com/llvm/llvm-project/commit/a733c6c7bb1c533ec28c96c49d3c5de7babd8b7f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-16 (Mon, 16 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/test/Analysis/CostModel/RISCV/cast-half.ll
    M llvm/test/Analysis/CostModel/RISCV/cast.ll
    M llvm/test/Analysis/CostModel/RISCV/cmp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

  Log Message:
  -----------
  [TargetLowering][RISCV] Allow scalable non-simple EVTs to be split even if the element type isn't a legal scalar type. (#144007)

This fixes an inconsistency in i64 vector handling between RV32 and
RV64. Even if i64 isn't legal as a scalar, we should still be able
to split a large i64 vector to get down to a legal vector type. We only
need to give up if we need to split a vscale x 1 vector.



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