[all-commits] [llvm/llvm-project] 7d9a45: [RISCV] Change input register type for QC_SWM and ...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d9a451d875368baece310ca7226e3adbc00e1bf
      https://github.com/llvm/llvm-project/commit/7d9a451d875368baece310ca7226e3adbc00e1bf
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-06-16 (Mon, 16 Jun 2025)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/MC/RISCV/xqcilsm-invalid.s

  Log Message:
  -----------
  [RISCV] Change input register type for QC_SWM and QC_SWMI (#144294)

Version 0.13 of the `Xqci` spec changes the register type of input
operand `rs3` from `GPR` to `GPRNoX0` for these two instructions.

The spec can be found at
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0



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