[all-commits] [llvm/llvm-project] 3fb6d8: MinSize = XLen + 1

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-support-non-power-of-2-types-when-expanding-memcmp
  Home:   https://github.com/llvm/llvm-project
  Commit: 3fb6d8a32231e8b77f926eda89886f47d77c3e1d
      https://github.com/llvm/llvm-project/commit/3fb6d8a32231e8b77f926eda89886f47d77c3e1d
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2025-06-16 (Mon, 16 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

  Log Message:
  -----------
  MinSize = XLen + 1

Created using spr 1.3.6-beta.1



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