[all-commits] [llvm/llvm-project] ecdb54: [TableGen] Avoid evaluating RHS of a BinOp until s...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecdb549e6de60b3211cfa860eec498270e3980f1
      https://github.com/llvm/llvm-project/commit/ecdb549e6de60b3211cfa860eec498270e3980f1
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-06-13 (Fri, 13 Jun 2025)

  Changed paths:
    M llvm/lib/TableGen/Record.cpp
    M llvm/test/TableGen/true-false.td

  Log Message:
  -----------
  [TableGen] Avoid evaluating RHS of a BinOp until short-circuit is complete (#144021)

This patch adds an even more aggressive short-circuit on `!and` and
`!or` that completely avoids the evaluation of RHS operand until short
circuiting decisions are made.



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