[all-commits] [llvm/llvm-project] 171152: Change to XLen + 1

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-support-non-power-of-2-types-when-expanding-memcmp
  Home:   https://github.com/llvm/llvm-project
  Commit: 17115212f1d7af68f5374896d1ddadf464b2bc11
      https://github.com/llvm/llvm-project/commit/17115212f1d7af68f5374896d1ddadf464b2bc11
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2025-06-13 (Fri, 13 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll

  Log Message:
  -----------
  Change to XLen + 1

Created using spr 1.3.6-beta.1



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