[all-commits] [llvm/llvm-project] 3f0cf7: [C++20] [Modules] [Reduced BMI] Don't write specia...
Nicolas Vasilache via All-commits
all-commits at lists.llvm.org
Thu Jun 12 03:34:34 PDT 2025
Branch: refs/heads/users/nico/transfer-read-after-write-broadcast-tightening
Home: https://github.com/llvm/llvm-project
Commit: 3f0cf742ac4eb3437450f8f263081ea951248851
https://github.com/llvm/llvm-project/commit/3f0cf742ac4eb3437450f8f263081ea951248851
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/pr119947.cppm
Log Message:
-----------
[C++20] [Modules] [Reduced BMI] Don't write specializations with local args
Close https://github.com/llvm/llvm-project/issues/119947
As discussed in the above thread, we shouldn't write specializations
with local args in reduced BMI. Since users can't find such
specializations any way.
Commit: 6157028fea93ff14af18b173dd01eb431cfb6aef
https://github.com/llvm/llvm-project/commit/6157028fea93ff14af18b173dd01eb431cfb6aef
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/test/Analysis/BasicAA/gep-decomposition-limit.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Transforms/Inline/inline-noalias-unidentify-object.ll
Log Message:
-----------
[BasicAA][ValueTracking] Increase depth for underlying object search (#143714)
This depth limits a linear search (rather than the usual potentially
exponential one) and is not particularly important for compile-time in
practice.
The change in #137297 is going to increase the length of GEP chains, so
I'd like to increase this limit a bit to reduce the chance of
regressions (https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2419
showed a 13% increase in SearchLimitReached). There is no particular
significance to the new value of 10.
Compile-time is neutral.
Commit: 77062244ed56be61aecda28d6fede3432545f741
https://github.com/llvm/llvm-project/commit/77062244ed56be61aecda28d6fede3432545f741
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Log Message:
-----------
Fix two instances of -Wparentheses warnings [NFC]
Add parentheses around the assert conditions.
Without this gcc warned like
../lib/Target/AMDGPU/GCNSchedStrategy.cpp:2250: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
2250 | NewMI != RegionBounds.second && "cannot remove at region end");
and
../../clang/lib/Sema/SemaOverload.cpp:11326:39: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
11326 | DeferredCandidatesCount == 0 &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
11327 | "Unexpected deferred template candidates");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 2d35b568ef949717e35df664d4d9352eddbffbfd
https://github.com/llvm/llvm-project/commit/2d35b568ef949717e35df664d4d9352eddbffbfd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/test/CodeGen/X86/bsf.ll
Log Message:
-----------
[X86] bsf.ll - add icmp_ne coverage to bsf passthrough tests
Commit: 6e5a1423b752c66273bfcff35aaa8083075788a8
https://github.com/llvm/llvm-project/commit/6e5a1423b752c66273bfcff35aaa8083075788a8
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
M mlir/test/Dialect/Linalg/simplify-pack-unpack.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
M mlir/unittests/Dialect/Utils/CMakeLists.txt
A mlir/unittests/Dialect/Utils/ReshapeOpsUtilsTest.cpp
Log Message:
-----------
[mlir] Reapply "Loosen restrictions on folding dynamic reshapes" (#142827)
The original PR https://github.com/llvm/llvm-project/pull/137963 had a
nvidia bot failure. This appears to be a flaky test because rerunning
the build was successful.
This change needs commit 6f2ba47 to fix incorrect usage of
`getReassociationIndicesForCollapse`.
Reverts llvm/llvm-project#142639
Co-authored-by: Artem Gindinson <gindinson at roofline.ai>
Commit: edaac11df3f82268e8ca34bf34b3e9d115b7d475
https://github.com/llvm/llvm-project/commit/edaac11df3f82268e8ca34bf34b3e9d115b7d475
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
M llvm/test/CodeGen/X86/pr132844.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineSelect - attempt to combine with shuffles (#143753)
Before legalization we will convert to a vector_shuffle node - but afterward we can try to combine the select into an existing target shuffle chain
Commit: 4079ed3c9e72d64746c5d3f05fc585d844c1e8a7
https://github.com/llvm/llvm-project/commit/4079ed3c9e72d64746c5d3f05fc585d844c1e8a7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
ARM: Move setting of more runtime libcalls to RuntimeLibcallInfo (#143826)
These are the easy cases that do not really depend on the subtarget,
other than for the deceptive predicates on the subtarget class. Most
of the rest of the cases here also do not, but this is obscured by
going through helper predicates added onto the subtarget which hide
dependence on TargetOptions.
Commit: 5434b85d2c7a83d9cebae06dad2f9d630e9a3927
https://github.com/llvm/llvm-project/commit/5434b85d2c7a83d9cebae06dad2f9d630e9a3927
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
Log Message:
-----------
ARM: Remove fake entries for divrem libcalls (#143832)
This was defining aliases of the i32 divrem functions for the i8
and i16 cases. This is unnecessary and was unused. The divrem
candidate cases wouldn't have formed with illegal types in the
first place, so codegen wouldn't even query these.
Commit: ce621041c2f162c50d630810491c2feee8eb6c64
https://github.com/llvm/llvm-project/commit/ce621041c2f162c50d630810491c2feee8eb6c64
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
Log Message:
-----------
[RISCV] Get host CPU name via hwprobe (#142745)
We can get the `mvendorid/marchid/mimpid` via hwprobe and then we
can compare these IDs with those defined in processors to find the
CPU name.
With this change, `-mcpu/-mtune=native` can set the proper name.
Commit: 4551e5035565606eb04253a35f31d51685657436
https://github.com/llvm/llvm-project/commit/4551e5035565606eb04253a35f31d51685657436
Author: kadir çetinkaya <kadircet at google.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Diagnostic.h
M clang/lib/Basic/Diagnostic.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
Log Message:
-----------
[clang] Reset FileID based diag state mappings (#143695)
When sharing same compiler instance for multiple compilations, we reset
source manager's file id tables in between runs. Diagnostics engine
keeps a cache based on these file ids, that became dangling references
across compilations.
This patch makes sure we reset those whenever sourcemanager is trashing
its FileIDs.
Commit: db8d34db26e9ea92c08d6e813eca9cce40c48478
https://github.com/llvm/llvm-project/commit/db8d34db26e9ea92c08d6e813eca9cce40c48478
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Set branch weight metadata on middle term in VPlan (NFC) (#143035)
Manage branch weights for the BranchOnCond in the middle block in VPlan.
This requires updating VPInstruction to inherit from VPIRMetadata, which
in general makes sense as there are a number of opcodes that could take
metadata.
There are other branches (part of the skeleton) that also need branch
weights adding.
PR: https://github.com/llvm/llvm-project/pull/143035
Commit: 2a27c059eccd96b6e46464dbdf69fd2f6237a56c
https://github.com/llvm/llvm-project/commit/2a27c059eccd96b6e46464dbdf69fd2f6237a56c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bsr.ll
M llvm/test/CodeGen/X86/pr40090.ll
Log Message:
-----------
[X86] Use BSR passthrough behaviour to fold (CMOV (BSR ?, X), Y, (X == 0)) -> (BSR Y, X) (#143662)
Make use of targets that support BSR "pass through behaviour" on a zero input to remove a CMOV thats performing the same function
BSF will be a trickier patch as we need to make sure it works with the "REP BSF" hack in X86MCInstLower
Commit: 1d1f9afe911c360b9505b5fd2c712cb112c8aa5f
https://github.com/llvm/llvm-project/commit/1d1f9afe911c360b9505b5fd2c712cb112c8aa5f
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaModule.cpp
A clang/test/Modules/pr143788.cppm
Log Message:
-----------
[C++20] [Modules] Treat directly imported internal partition unit as reachable
Close https://github.com/llvm/llvm-project/issues/143788
See the discussion for details.
Commit: 8e4fdff6f02161d878a63900abb35aaa32ff85e9
https://github.com/llvm/llvm-project/commit/8e4fdff6f02161d878a63900abb35aaa32ff85e9
Author: Omair Javaid <omair.javaid at linaro.org>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/test/CodeGen/X86/tailcc-ssp.ll
Log Message:
-----------
[X86] Update tailcc-ssp.ll assertions using update_llc_test_checks.py (#143500)
The assertions in llvm/test/CodeGen/X86/tailcc-ssp.ll were outdated. The
initial comment indicated they were generated with
`utils/update_llc_test_checks.py UTC_ARGS: --version 5`, but this was
not accurate based on the file's content.
Running `utils/update_llc_test_checks.py` regenerated the assertions,
aligning them with the current `llc` output.
This commit ensures that the test's claimed behavior accurately reflects
the actual `llc` output, even though the tests were already passing.
This was identified by @efriedma-quic during review of #136290.
Submitting a separate PR to make sure these changes stay isolated.
Commit: 3e5d50f9c61bb266ab17919ab5209c7b08520aff
https://github.com/llvm/llvm-project/commit/3e5d50f9c61bb266ab17919ab5209c7b08520aff
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-invalid.ll
Log Message:
-----------
[NVPTX] Add cta_group support to TMA G2S intrinsics (#143178)
This patch extends the TMA G2S intrinsics with the
support for cta_group::1/2 available from Blackwell onwards.
The existing intrinsics are auto-upgraded with a default
value of '0' for the `cta_group` flag operand.
* lit tests are added for all combinations of the newer variants.
* Negative tests are added to validate the error-handling
when the value of the cta_group flag falls out-of-range.
* The generated PTX is verified with a 12.8 ptxas executable.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: a8c6fb4cb8e686f733e022afc549bc085d1558f4
https://github.com/llvm/llvm-project/commit/a8c6fb4cb8e686f733e022afc549bc085d1558f4
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/test/Analysis/ScopedNoAliasAA/alias-scope-merging.ll
M llvm/test/Transforms/MemCpyOpt/callslot_badaa.ll
Log Message:
-----------
[MemCpyOpt] Fix lifetime marker sizes in tests (NFC)
As pointed out in https://github.com/llvm/llvm-project/pull/143782,
these tests were specifying the size in bits instead of bytes.
In order to preserve the intent of the tests, add a use of %src,
which prevents stack-move optimization. These are supposed to test
the handling of scoped alias metadata in call slot optimization.
Commit: 5987f1ee5cc59a05961156c04010ab0f3c857628
https://github.com/llvm/llvm-project/commit/5987f1ee5cc59a05961156c04010ab0f3c857628
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/narrow-switch.ll
Log Message:
-----------
[InstCombine] Regenerate `narrow-switch.ll` test (NFC)
`narrow-switch.ll` test has been regenerated via latest UTC using
`--prefix-filecheck-ir-name _`, so as to avoid conflicts with
scripted variable names.
Commit: 7ef77eb9984d1fb537a409cf4be89560fbb681fe
https://github.com/llvm/llvm-project/commit/7ef77eb9984d1fb537a409cf4be89560fbb681fe
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
Log Message:
-----------
[LV] Support scalable interleave groups for factors 3,5,6 and 7 (#141865)
Currently the loop vectorizer can only vectorize interleave groups for
power-of-2 factors at scalable VFs by recursively interleaving
[de]interleave2 intrinsics.
However after https://github.com/llvm/llvm-project/pull/124825 and
#139893, we now have [de]interleave intrinsics for all factors up to 8,
which is enough to support all types of segmented loads and stores on
RISC-V.
Now that the interleaved access pass has been taught to lower these in
#139373 and #141512, this patch teaches the loop vectorizer to emit
these intrinsics for factors up to 8, which enables scalable
vectorization for non-power-of-2 factors.
As far as I'm aware, no in-tree target will vectorize a scalable
interelave group above factor 8 because the maximum interleave factor is
capped at 4 on AArch64 and 8 on RISC-V, and the
`-max-interleave-group-factor` CLI option defaults to 8, so the
recursive [de]interleaving code has been removed for now.
Factors of 3 with scalable VFs are also turned off in AArch64 since
there's no lowering for [de]interleave3 just yet either.
Commit: 702b9033c115500a934a6c49c325c112b30fe47f
https://github.com/llvm/llvm-project/commit/702b9033c115500a934a6c49c325c112b30fe47f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Log Message:
-----------
[LLVM][CodeGen][AArch64] Lower vector-(de)interleave to multi-register uzp/zip instructions. (#143128)
Commit: d517f15e09e49e172387cb6deb76e4ee2d45d0e4
https://github.com/llvm/llvm-project/commit/d517f15e09e49e172387cb6deb76e4ee2d45d0e4
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/test/Transforms/LICM/call-hoisting.ll
Log Message:
-----------
[LICM] Regenerate test checks (NFC)
Commit: 971c49fbf361c22ccf20913f61a58c28b26c4e27
https://github.com/llvm/llvm-project/commit/971c49fbf361c22ccf20913f61a58c28b26c4e27
Author: SahilPatidar <patidarsahil2001 at gmail.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/fneg.ll
M llvm/test/Transforms/InstCombine/fsub.ll
Log Message:
-----------
[InstCombine] Ensure Safe Handling of Flags in foldFNegIntoConstant (#94148)
Fix #93769
alive2: https://alive2.llvm.org/ce/z/MHShQY
Commit: 612c9ca54c6559d9e9137bbc8a64acb7c89cfa4e
https://github.com/llvm/llvm-project/commit/612c9ca54c6559d9e9137bbc8a64acb7c89cfa4e
Author: Nicolas Vasilache <nicolasvasilache at users.noreply.github.com>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Diagnostic.h
M clang/lib/Basic/Diagnostic.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/pr119947.cppm
A clang/test/Modules/pr143788.cppm
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/BasicAA/gep-decomposition-limit.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Analysis/ScopedNoAliasAA/alias-scope-merging.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-invalid.ll
M llvm/test/CodeGen/X86/bsf.ll
M llvm/test/CodeGen/X86/bsr.ll
M llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
M llvm/test/CodeGen/X86/pr132844.ll
M llvm/test/CodeGen/X86/pr40090.ll
M llvm/test/CodeGen/X86/tailcc-ssp.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/Transforms/Inline/inline-noalias-unidentify-object.ll
M llvm/test/Transforms/InstCombine/fneg.ll
M llvm/test/Transforms/InstCombine/fsub.ll
M llvm/test/Transforms/InstCombine/narrow-switch.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/MemCpyOpt/callslot_badaa.ll
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
M mlir/test/Dialect/Linalg/simplify-pack-unpack.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
M mlir/unittests/Dialect/Utils/CMakeLists.txt
A mlir/unittests/Dialect/Utils/ReshapeOpsUtilsTest.cpp
Log Message:
-----------
Merge branch 'main' into users/nico/transfer-read-after-write-broadcast-tightening
Compare: https://github.com/llvm/llvm-project/compare/50589c05f71e...612c9ca54c65
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