[all-commits] [llvm/llvm-project] e7e491: [SelectionDAG] Add ISD::VSELECT to SelectionDAG::c...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7e491f6ee2baee4e2ab2947e1c64bc54e3ebbec
      https://github.com/llvm/llvm-project/commit/e7e491f6ee2baee4e2ab2947e1c64bc54e3ebbec
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-11 (Wed, 11 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
    M llvm/test/CodeGen/X86/avx10_2bf16-arith.ll

  Log Message:
  -----------
  [SelectionDAG] Add ISD::VSELECT to SelectionDAG::canCreateUndefOrPoison. (#143760)



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