[all-commits] [llvm/llvm-project] 806333: [RISCV] Guard the alternative static chain registe...

[Jesse Huang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 806333063ff9a09ca001dcd77d4d5d6f0b9ecd74
      https://github.com/llvm/llvm-project/commit/806333063ff9a09ca001dcd77d4d5d6f0b9ecd74
  Author: Jesse Huang <jesse.huang at sifive.com>
  Date:   2025-06-12 (Thu, 12 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/test/CodeGen/RISCV/nest-register.ll

  Log Message:
  -----------
  [RISCV] Guard the alternative static chain register use on ILP32E/LP64E (#142715)

Asserts the use of t3(x28) as the static chain register when branch control flow protection is enabled with ILP32E/LP64E, because such register is not present within the ABI.



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