[all-commits] [llvm/llvm-project] 76e14d: [X86][BreakFalseDeps] Using reverse order for unde...

[Phoebe Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76e14deb4a6967388a9bf84db2feeac17a30c786
      https://github.com/llvm/llvm-project/commit/76e14deb4a6967388a9bf84db2feeac17a30c786
  Author: Phoebe Wang <phoebe.wang at intel.com>
  Date:   2025-06-11 (Wed, 11 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/RegisterClassInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/BreakFalseDeps.cpp
    M llvm/lib/CodeGen/RegisterClassInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/test/CodeGen/X86/avx-cvt.ll
    M llvm/test/CodeGen/X86/avx512-cvt.ll
    M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
    M llvm/test/CodeGen/X86/avx512fp16-cvt.ll
    M llvm/test/CodeGen/X86/avx512fp16-novl.ll
    M llvm/test/CodeGen/X86/break-false-dep.ll
    M llvm/test/CodeGen/X86/coalescer-commute1.ll
    M llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
    M llvm/test/CodeGen/X86/fast-isel-int-float-conversion-x86-64.ll
    M llvm/test/CodeGen/X86/fast-isel-int-float-conversion.ll
    M llvm/test/CodeGen/X86/fast-isel-uint-float-conversion-x86-64.ll
    M llvm/test/CodeGen/X86/fast-isel-uint-float-conversion.ll
    M llvm/test/CodeGen/X86/fcmp-logic.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/fold-load-unops.ll
    M llvm/test/CodeGen/X86/fp-intrinsics.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-round-fp16.ll
    M llvm/test/CodeGen/X86/ftrunc.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/isel-int-to-fp.ll
    M llvm/test/CodeGen/X86/pr34080.ll
    M llvm/test/CodeGen/X86/pr37879.ll
    M llvm/test/CodeGen/X86/pr38803.ll
    M llvm/test/CodeGen/X86/rounding-ops.ll
    M llvm/test/CodeGen/X86/scalar-int-to-fp.ll
    M llvm/test/CodeGen/X86/select-narrow-int-to-fp.ll
    M llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
    M llvm/test/CodeGen/X86/sse-cvttp2si.ll
    M llvm/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
    M llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
    M llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll
    M llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll
    M llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
    M llvm/test/CodeGen/X86/vec_int_to_fp.ll
    M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [X86][BreakFalseDeps] Using reverse order for undef register selection (#137569)

BreakFalseDeps picks the best register for undef operands if
instructions have false dependency. The problem is if the instruction is
close to the beginning of the function, ReachingDefAnalysis is over
optimism to the unused registers, which results in collision with
registers just defined in the caller.

This patch changes the selection of undef register in an reverse order,
which reduces the probability of register collisions between caller and
callee. It brings improvement in some of our internal benchmarks with
negligible effect on other benchmarks.



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