[all-commits] [llvm/llvm-project] 332a73: [SelectionDAG] Deal with POISON for INSERT_VECTOR_...

[Björn Pettersson via All-commits]

  Branch: refs/heads/users/bjope/insertundef_3
  Home:   https://github.com/llvm/llvm-project
  Commit: 332a73f2f91369ccd03155a276d0e439e243563a
      https://github.com/llvm/llvm-project/commit/332a73f2f91369ccd03155a276d0e439e243563a
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll
    M llvm/test/CodeGen/X86/mmx-build-vector.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/pr62286.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/vector-trunc.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll

  Log Message:
  -----------
  [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2)

Add support in isGuaranteedNotToBeUndefOrPoison and
SimplifyDemandedVectorElts to avoid regressions
seen after a previous commit fixing #141034.



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