[all-commits] [llvm/llvm-project] d56ce3: [Clang] Non-polymorphic trivially relocatable type...

Tue Jun 10 00:37:19 PDT 2025

  Branch: refs/heads/users/boomanaiden154/main.ci-refactor-out-some-early-exits-in-compute_projects
  Home:   https://github.com/llvm/llvm-project
  Commit: d56ce312d0c2e5ae74476977a8952dbb3ba4c513
      https://github.com/llvm/llvm-project/commit/d56ce312d0c2e5ae74476977a8952dbb3ba4c513
  Author: Corentin Jabot <corentinjabot at gmail.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M clang/include/clang/Sema/Sema.h
    M clang/lib/Sema/SemaDeclCXX.cpp
    M clang/lib/Sema/SemaTypeTraits.cpp
    M clang/test/SemaCXX/attr-trivial-abi.cpp
    M clang/test/SemaObjCXX/attr-trivial-abi.mm

  Log Message:
  -----------
  [Clang] Non-polymorphic trivially relocatable types can have [[trivial_abi]] (#143111)

Use the definition of trivially relocatable types to short-circuit some
checks for trivial_abi.

Note that this is mostly a no-op as there is a lot of overlap between
trivial_abi and trivial relocatability (ie, I can't envision a scenario
in which there would be a trivially relocatable type that would not be
eligible for trivial_abi based on its special member function... which
is good!)

Note that for bases and members, we need to check CanPassInRegister
rather than just relocation. So we do these checks first, which leads to
better diagnostics.

  Commit: 6881c7d5fad8182116e41cc8fc061773afd5ec88
      https://github.com/llvm/llvm-project/commit/6881c7d5fad8182116e41cc8fc061773afd5ec88
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/reassoc-shl-addi-add.ll

  Log Message:
  -----------
  [RISCV] Don't select sh{1,2,3}add if shl doesn't have one use (#143351)

Try to fix https://github.com/llvm/llvm-project/pull/130829#pullrequestreview-2730533158.
There's no benefit if shl doesn't have one use.

  Commit: 5f648c370edf5d71c471ffbabdaaa821ad05fb4b
      https://github.com/llvm/llvm-project/commit/5f648c370edf5d71c471ffbabdaaa821ad05fb4b
  Author: David Green <david.green at arm.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M clang/lib/CodeGen/Targets/AArch64.cpp
    M clang/test/CodeGen/AArch64/struct-coerce-using-ptr.cpp
    M clang/test/CodeGen/ptrauth-in-c-struct.c
    M clang/test/CodeGenCXX/ptrauth-qualifier-struct.cpp
    M clang/test/CodeGenCXX/trivial_abi.cpp

  Log Message:
  -----------
  [AArch64] Change the coercion type of structs with pointer members. (#135064)

The aim here is to avoid a ptrtoint->inttoptr round-trip through the function
argument whilst keeping the calling convention the same. Given a struct which
is <= 128bits in size, which can only contain either 1 or 2 pointers, we
convert to a ptr or [2 x ptr] as opposed to the old coercion that uses i64 or
[2 x i64]. This helps alias analysis produce more accurate results.

  Commit: bfe096760345fb040138e10a2884b95fbd812dc9
      https://github.com/llvm/llvm-project/commit/bfe096760345fb040138e10a2884b95fbd812dc9
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Remove the TODO for vqdotsu. NFC.

It has been supported by #141267.

  Commit: 487e757f3e587aedc1668fb9cb18a8d464913605
      https://github.com/llvm/llvm-project/commit/487e757f3e587aedc1668fb9cb18a8d464913605
  Author: Oliver Hunt <oliver at apple.com>
  Date:   2025-06-09 (Mon, 09 Jun 2025)

  Changed paths:
    M clang/lib/CodeGen/CGExprCXX.cpp

  Log Message:
  -----------
  [clang][NFC] Remove dead PassTypeToPlacementDelete field (#143448)

The CallDeleteDuringNew::PassTypeToPlacementDelete field became unneeded
during the many refactorings of P2719 but I didn't actually remove it.

  Commit: 530f5b779111034da78c3419eeda7a360c101755
      https://github.com/llvm/llvm-project/commit/530f5b779111034da78c3419eeda7a360c101755
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86] LowerStore - always split 512-bit concatenated stores (#143426)

All BWI regressions have now been addressed, so remove the special case
handling.

  Commit: 0c3a7725375ec583147429cc367320f0e8506847
      https://github.com/llvm/llvm-project/commit/0c3a7725375ec583147429cc367320f0e8506847
  Author: Piotr Fusik <p.fusik at samsung.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV][test] Add tests for add.uw with a constant

  Commit: 77347d6513de6a6f5dee8ade76e0a0ad1552c12b
      https://github.com/llvm/llvm-project/commit/77347d6513de6a6f5dee8ade76e0a0ad1552c12b
  Author: Martin Storsjö <martin at martin.st>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    R llvm/test/tools/llvm-rc/Inputs/tag-accelerators-ascii-alt.rc
    M llvm/test/tools/llvm-rc/Inputs/tag-accelerators.rc
    M llvm/test/tools/llvm-rc/tag-accelerators.test
    M llvm/tools/llvm-rc/ResourceFileWriter.cpp

  Log Message:
  -----------
  [llvm-rc] Allow ALT on non-virtkey accelerators (#143374)

While
https://learn.microsoft.com/en-us/windows/win32/menurc/accelerators-resource
specifies that ALT only applies to virtkeys, this doesn't seem to be the
case in reality.

https://learn.microsoft.com/en-us/windows/win32/menurc/using-keyboard-accelerators
contains an example that uses this combination:

    "B",   ID_ACCEL5, ALT                   ; ALT_SHIFT+B

Also Microsoft also includes such cases in their repo of test cases:
https://github.com/microsoft/Windows-classic-samples/blob/263dd514ad215d0a40d1ec44b4df84b30ec11dcf/Samples/Win7Samples/begin/sdkdiff/sdkdiff.rc#L161-L164

Also MS rc.exe doesn't warn/error about this. However if applying SHIFT
or CONTROL on a non-virtkey accelerator, MS rc.exe does produce this
warning:

    warning RC4203 : SHIFT or CONTROL used without VIRTKEY

Hence, keep the checks for SHIFT and CONTROL, but remove the checks for
ALT, which seems to have been incorrect.

This fixes one aspect of
https://github.com/llvm/llvm-project/issues/143157.

  Commit: ecc8b29eda2acc517170e9dde212986ad677cc68
      https://github.com/llvm/llvm-project/commit/ecc8b29eda2acc517170e9dde212986ad677cc68
  Author: Henrich Lauko <xlauko at mail.muni.cz>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

  Log Message:
  -----------
  [CIR][NFC] Use actual operand name in adaptor-obtained operands (#143028)

This mirrors incubator changes from https://github.com/llvm/clangir/pull/1661

  Commit: 20e8de9c8f4cf54c6c57535428c987d921861034
      https://github.com/llvm/llvm-project/commit/20e8de9c8f4cf54c6c57535428c987d921861034
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    M llvm/test/Transforms/InstCombine/icmp.ll
    M llvm/test/Transforms/InstCombine/sub-gep.ll

  Log Message:
  -----------
  [InstCombine] Support nested GEPs in OptimizePointerDifference (#142958)

Currently OptimizePointerDifference() only handles single GEPs with a
common base, not GEP chains. This patch generalizes the support to
nested GEPs with a common base.

Finding the common base is a bit annoying because we want to stop as
soon as possible and not recurse into common GEP prefixes.

This helps avoids regressions from
https://github.com/llvm/llvm-project/pull/137297.

  Commit: e5ff7055beb116f103f030d992fadea49c994511
      https://github.com/llvm/llvm-project/commit/e5ff7055beb116f103f030d992fadea49c994511
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Transforms/Utils/LoopPeel.cpp
    M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll

  Log Message:
  -----------
  [LoopPeel] Use loop guards when checking if last iter can be peeled. (#142605)

Apply loop guards to BTC before checking if the last iteration should be
peeled off. This also adds an assert to make sure applying the guards
does not pessimize the results. I checked on a large test set and it did
not trigger there, but it adds an additional guard to catch potential
cases where loop-guards pessimize results.

Peels ~15% more loops.

PR: https://github.com/llvm/llvm-project/pull/142605

  Commit: 6a8464b1251ae6cf01eb3af34441e3ce714a5542
      https://github.com/llvm/llvm-project/commit/6a8464b1251ae6cf01eb3af34441e3ce714a5542
  Author: Phoebe Wang <phoebe.wang at intel.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    R llvm/test/CodeGen/X86/avx512fp16-cvt-novl.ll
    A llvm/test/CodeGen/X86/avx512fp16-novl.ll

  Log Message:
  -----------
  [X86][FP16] Do not generate X86 FMIN/FMAX for FP16 when VLX not enabled, part 2 (#143483)

Fixes: https://godbolt.org/z/eYTxeqE48

  Commit: f0d05b973b0d09521aad00d3aec36e4478626cc2
      https://github.com/llvm/llvm-project/commit/f0d05b973b0d09521aad00d3aec36e4478626cc2
  Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/IR/LLVMContextImpl.h

  Log Message:
  -----------
  [NFC][DebugInfo] Make MDNodeKeyImpl<DILocation>::Column 16 bits (#143399)

Column is limited to 16 bits in several places in the compiler:
DebugInfoMetadata.cpp#L87, LLParser.cpp#L4706, and more

Slight compile time improvement due to reducing `hash_combine` workload
in `MDNodeKeyImpl<DILocation>::getHashValue()`.

Positively affects compile time regardless of whether Key Instructions
is enabled. See PR for numbers.

  Commit: 4cafd28b7dd92080103d11cccc78d9a2f01e1242
      https://github.com/llvm/llvm-project/commit/4cafd28b7dd92080103d11cccc78d9a2f01e1242
  Author: Aiden Grossman <agrossman154 at yahoo.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    R lld/test/COFF/lto-late-arm.ll

  Log Message:
  -----------
  [lld] Delete lto-late-arm.ll

This test is failing on a couple of bots and on premerge after
a082f665f85b1002ab22af263eeafceca5288657.

That patch configures the relevant libcalls for ARM in RuntimeLibCalls.
This causes __rt_sdiv to get pulled into the LTO preopt IR. This should
happen for other builtins as well, which means that the original issue
that the patch introducing this patch intended to diagnose should no
longer exist.

The compiler generated calls to builtins mentioned in
7f9a0048fa3fb5513c09731a7f82a851b0bcd609 should always have definitions,
assuming they are available in the link and will not only get pulled in
late if lazily loading symbols from archives. We otherwise get the
standard diagnostic if they are not.

  Commit: 1a30526afb7adf0514141193a2a471fc2d1d614d
      https://github.com/llvm/llvm-project/commit/1a30526afb7adf0514141193a2a471fc2d1d614d
  Author: Aiden Grossman <aidengrossman at google.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M clang/include/clang/Sema/Sema.h
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
    M clang/lib/CodeGen/CGExprCXX.cpp
    M clang/lib/CodeGen/Targets/AArch64.cpp
    M clang/lib/Sema/SemaDeclCXX.cpp
    M clang/lib/Sema/SemaTypeTraits.cpp
    M clang/test/CodeGen/AArch64/struct-coerce-using-ptr.cpp
    M clang/test/CodeGen/ptrauth-in-c-struct.c
    M clang/test/CodeGenCXX/ptrauth-qualifier-struct.cpp
    M clang/test/CodeGenCXX/trivial_abi.cpp
    M clang/test/SemaCXX/attr-trivial-abi.cpp
    M clang/test/SemaObjCXX/attr-trivial-abi.mm
    R lld/test/COFF/lto-late-arm.ll
    M llvm/lib/IR/LLVMContextImpl.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    M llvm/lib/Transforms/Utils/LoopPeel.cpp
    M llvm/test/CodeGen/RISCV/reassoc-shl-addi-add.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    R llvm/test/CodeGen/X86/avx512fp16-cvt-novl.ll
    A llvm/test/CodeGen/X86/avx512fp16-novl.ll
    M llvm/test/Transforms/InstCombine/icmp.ll
    M llvm/test/Transforms/InstCombine/sub-gep.ll
    M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll
    R llvm/test/tools/llvm-rc/Inputs/tag-accelerators-ascii-alt.rc
    M llvm/test/tools/llvm-rc/Inputs/tag-accelerators.rc
    M llvm/test/tools/llvm-rc/tag-accelerators.test
    M llvm/tools/llvm-rc/ResourceFileWriter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]

Compare: https://github.com/llvm/llvm-project/compare/78d8f901fb9d...1a30526afb7a

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications