[all-commits] [llvm/llvm-project] 34b985: [RISCV] Select unsigned bitfield extract for Xqcib...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34b985f635a734e7e513ea2196f3010b9c3cc6ae
      https://github.com/llvm/llvm-project/commit/34b985f635a734e7e513ea2196f3010b9c3cc6ae
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/xqcibm-extract.ll

  Log Message:
  -----------
  [RISCV] Select unsigned bitfield extract for Xqcibm (#143354)

The Xqcibm Bit Manipulation extension has the `qc.extu` instruction that
can extract a subset of bits from the source register to the destination
register.

Unlike the corresponding instructions in XTHeadbb and XAndesPerf which
extract the bits between `Msb` and `Lsb`, the `qc.extu` instruction
extracts `width` bits from an offset that is determined by the `shamt`.



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