[all-commits] [llvm/llvm-project] 5cd1f4: AMDGPU: Try constant fold after folding immediate

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/si-peephole-opt-try-constant-fold-after-imm-fold
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cd1f4ca4de989b55d4308eb6b65b007a1549550
      https://github.com/llvm/llvm-project/commit/5cd1f4ca4de989b55d4308eb6b65b007a1549550
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-06-10 (Tue, 10 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
    M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll

  Log Message:
  -----------
  AMDGPU: Try constant fold after folding immediate

This helps avoid some regressions in a future patch. The or 0
pattern appears in the division tests because the reduce 64-bit
bit operation to a 32-bit one with half identity value is only
implemented for constants. We could fix that by using computeKnownBits.
Additionally the pattern disappears if I optimize the IR division
expansion, so that IR should probably be emitted more optimally in
the first place.



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