[all-commits] [llvm/llvm-project] 61cdba: [AArch64][GlobalISel] Expand 64bit extracts to 128...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 61cdba602abe67761ab2bbf12bf85710dfa963f4
      https://github.com/llvm/llvm-project/commit/61cdba602abe67761ab2bbf12bf85710dfa963f4
  Author: David Green <david.green at arm.com>
  Date:   2025-06-09 (Mon, 09 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
    M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/abs.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
    M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/double_reduct.ll
    M llvm/test/CodeGen/AArch64/f16-instructions.ll
    M llvm/test/CodeGen/AArch64/faddsub.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fcvt.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fminimummaximum.ll
    M llvm/test/CodeGen/AArch64/fminmax.ll
    M llvm/test/CodeGen/AArch64/fmla.ll
    M llvm/test/CodeGen/AArch64/fmul.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptrunc.ll
    M llvm/test/CodeGen/AArch64/fsqrt.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/llvm.exp10.ll
    M llvm/test/CodeGen/AArch64/popcount.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/store.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
    M llvm/test/CodeGen/AArch64/vector-lrint.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Expand 64bit extracts to 128bit to allow more patterns (#142904)

SDAG will promote a 64bit G_EXTRACT_VECTOR_ELT to 128 to reduce the
number of duplicate lane-extract patterns needed. This patch does the
same for gisel inside regbankselect, so that selection will operate on
the larger vectors.

Most of the tests just add kill markers, but arm64-neon-v8.1a.ll shows the
lanewise patterns now being selected (which, as of this patch is now
fully producing the same code as SDAG).



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