[all-commits] [llvm/llvm-project] 939666: [SDAG] Add partial_reduce_sumla node (#141267)

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 939666380fba5d6db3d224fc358fd3e0f40a9b53
      https://github.com/llvm/llvm-project/commit/939666380fba5d6db3d224fc358fd3e0f40a9b53
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-06-09 (Mon, 09 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
    M llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll

  Log Message:
  -----------
  [SDAG] Add partial_reduce_sumla node (#141267)

We have recently added the partial_reduce_smla and partial_reduce_umla
nodes to represent Acc += ext(b) * ext(b) where the two extends have to
have the same source type, and have the same extend kind.

For riscv64 w/zvqdotq, we have the vqdot and vqdotu instructions which
correspond to the existing nodes, but we also have vqdotsu which
represents the case where the two extends are sign and zero respective
(i.e. not the same type of extend).

This patch adds a partial_reduce_sumla node which has sign extension for
A, and zero extension for B. The addition is somewhat mechanical.



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