[all-commits] [llvm/llvm-project] 645c0d: [AArch64][GlobalISel] Ensure we have a insert-subr...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 645c0d509c43ef95b62503552c51e57c6e49f0e0
      https://github.com/llvm/llvm-project/commit/645c0d509c43ef95b62503552c51e57c6e49f0e0
  Author: David Green <david.green at arm.com>
  Date:   2025-06-06 (Fri, 06 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
    M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/abs.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/arm64-fp128.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
    M llvm/test/CodeGen/AArch64/bitcast-extend.ll
    M llvm/test/CodeGen/AArch64/bitcast.ll
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/ctlz.ll
    M llvm/test/CodeGen/AArch64/cttz.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/freeze.ll
    M llvm/test/CodeGen/AArch64/fsh.ll
    M llvm/test/CodeGen/AArch64/icmp.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/mul.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/phi.ll
    M llvm/test/CodeGen/AArch64/popcount.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/rem.ll
    M llvm/test/CodeGen/AArch64/select_cc.ll
    M llvm/test/CodeGen/AArch64/sext.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/trunc.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll
    M llvm/test/CodeGen/AArch64/xtn.ll
    M llvm/test/CodeGen/AArch64/zext.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Ensure we have a insert-subreg v4i32 GPR pattern (#142724)

This is the GISel equivalent of scalar_to_vector, making sure that when
we insert into undef we use a fmov that avoids the artificial dependency
on the previous register. This adds v2i32 and v2i64 patterns too for
similar reasons.



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