[all-commits] [llvm/llvm-project] c95bc4: [AArch64][SDAG] Fix selection of extend of v1if16 ...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c95bc415620cc7e832f4e768030e6e6cb5f9d45e
      https://github.com/llvm/llvm-project/commit/c95bc415620cc7e832f4e768030e6e6cb5f9d45e
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-06-06 (Fri, 06 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll

  Log Message:
  -----------
  [AArch64][SDAG] Fix selection of extend of v1if16 SETCC (#140274)

There is a DAG combine, that folds:

```
t1: v1i1 = setcc x:v1f16, y:v1f16, setogt:ch
	t2: v1i64 = zero_extend t1
```

->

```
t1: v1i16 = setcc x:v1f16, y:v1f16, setogt:ch
	t2: v1i64 = any_extend t1
```

This creates an issue on AArch64 when attempting to widen the result to
`v4i16`. The operand types (`v1f16`) are set to be scalarized, so the
"by hand" widening with `DAG.WidenVector` is used for them, however,
this only widens to the next power-of-2, so returns `v2f16`, which does
not match the result VF. The fix is to manually construct the widened
inputs using `INSERT_SUBVECTOR`.

Fixes #136540



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