[all-commits] [llvm/llvm-project] d39504: [RISCV] Select unsigned bitfield insert for XAndes...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d3950433008cc524f0d93882f057026f88e346d8
      https://github.com/llvm/llvm-project/commit/d3950433008cc524f0d93882f057026f88e346d8
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-06 (Fri, 06 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/test/CodeGen/RISCV/rv32xandesperf.ll
    M llvm/test/CodeGen/RISCV/rv64xandesperf.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Select unsigned bitfield insert for XAndesPerf (#142737)

The XAndesPerf extension includes unsigned bitfield extraction
instruction `NDS.BFOZ`, which can extract the bits from 0 to Len -1,
place them starting at bit Msb, and zero-fills the remaining bits.

This patch handles the cases where Msb < Lsb for `NDS.BFOZ`.

Instruction Sytax:

    nds.bfoz Rd, Rs1, Msb, Lsb

The operation is:

    if Msb < Lsb:
        Lenm1 = Lsb - Msb;
        Rd[Lsb:Msb] = Rs1[Lenm1:0];
        if (Lsb < (XLen -1)) Rd[XLen-1:Lsb+1]=0;
        Rd[Msb-1:0]=0;

When Len == 1, it is a special case where the Msb is set to 0 instead of
being equal to the Lsb.



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