[all-commits] [llvm/llvm-project] 9fba20: [SiFive][RISCV] Remove VMConstraint from XSfvqmacc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fba20bfacc878bc89b89c1ff44805c5f8a142df
      https://github.com/llvm/llvm-project/commit/9fba20bfacc878bc89b89c1ff44805c5f8a142df
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-05 (Thu, 05 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/test/MC/RISCV/rvv/xsfvfwmacc.s
    M llvm/test/MC/RISCV/rvv/xsfvqmacc.s

  Log Message:
  -----------
  [SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. (#142914)

These instructions don't have a mask operand. The VMConstraint would
cause an assertion if V0 is used as the destination and the last
register isn't V0.



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