[all-commits] [llvm/llvm-project] feb21e: [RISCV] Add SiFive X390 processor definition (#142...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: feb21e26fa0eff9c977394f04c089ea887f63b9f
      https://github.com/llvm/llvm-project/commit/feb21e26fa0eff9c977394f04c089ea887f63b9f
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-06-04 (Wed, 04 Jun 2025)

  Changed paths:
    A clang/test/Driver/print-enabled-extensions/riscv-sifive-x390.c
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add SiFive X390 processor definition (#142517)

X390 is an in-order core designed for AI/ML workload, with VLEN=1024.
https://www.sifive.com/cores/intelligence-x300-series

Scheduling model will be added in a follow-up patch.



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