[all-commits] [llvm/llvm-project] 991d75: [RISCV] Implement base scheduling model for andes ...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 991d754074c187016c0159113ca64d0c55fe86c1
      https://github.com/llvm/llvm-project/commit/991d754074c187016c0159113ca64d0c55fe86c1
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-04 (Wed, 04 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedAndes45.td
    A llvm/test/tools/llvm-mca/RISCV/Andes45/fpr.s
    A llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s

  Log Message:
  -----------
  [RISCV] Implement base scheduling model for andes 45 series processor. (#141008)

This patch implements scheduling model for IMAFD and Zb extension. The
latency and throughput of all instructions, except load/store, are
measured by llvm-exegesis.

Scheduling model for V and other extensions will be added in a follow-up
patch.



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