[all-commits] [llvm/llvm-project] 88738a: [RISCV] Optimize two source deinterleave2 via ri.v...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88738a74f05ba4002f38b8bdeebd944762c8ae7b
      https://github.com/llvm/llvm-project/commit/88738a74f05ba4002f38b8bdeebd944762c8ae7b
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-06-03 (Tue, 03 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll

  Log Message:
  -----------
  [RISCV] Optimize two source deinterleave2 via ri.vunzip2{a,b} (#142667)

As done for the existing vnsrl cases, we can split a two source
deinterleave2 into two single source deinterleave2 and a slideup.  
We can also use a concat-then-deinterleave2 tactic. Both are equally
valid (except in the m8 source type case), and the 
concat-then-deinterleave2 saves one instruction for fractional LMUL cases.

Additionally, if we happen to know the exact VLEN and our fixed vectors
are an even number of vector registers, we can avoid the need to split or
concat entirely and just use both registers sources.



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