[all-commits] [llvm/llvm-project] 3d2650: [RISCV] Use addi rather than addiw for immediates ...
Alex Bradbury via All-commits
all-commits at lists.llvm.org
Mon Jun 2 14:25:11 PDT 2025
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3d2650bdeb8409563d917d8eef70b906323524ef
https://github.com/llvm/llvm-project/commit/3d2650bdeb8409563d917d8eef70b906323524ef
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-06-02 (Mon, 02 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/alu16.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/avgceilu.ll
M llvm/test/CodeGen/RISCV/avgflooru.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-imm.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-imm.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/imm.ll
M llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr58286.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr68855.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr90730.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/prefer-w-inst.ll
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/prolog-epilogue.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64xtheadba.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/pr88799.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shlimm-addimm.ll
M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue-nounwind.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/switch-width.ll
M llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/MC/RISCV/rv64c-aliases-valid.s
M llvm/test/MC/RISCV/rv64i-aliases-valid.s
M llvm/test/MC/RISCV/rv64zba-aliases-valid.s
M llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
Log Message:
-----------
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
The logic in RISCVMatInt would previously produce lui+addiw on RV64
whenever a 32-bit integer must be materialised and the Hi20 and Lo12
parts are non-zero. However, sometimes addi can be used equivalently
(whenever the sign extension behaviour of addiw would be a no-op). This
patch moves to using addiw only when necessary. Although there is
absolutely no advantage in terms of compressibility or performance, this
has the following advantages:
* It's more consistent with logic used elsewhere in the backend. For
instance, RISCVOptWInstrs will try to convert addiw to addi on the basis
it reduces test diffs vs RV32.
* This matches the lowering GCC does in its codegen path. Unlike LLVM,
GCC seems to have different expansion logic for the assembler vs
codegen. For codegen it will use lui+addi if possible, but expanding
`li` in the assembler will always produces lui+addiw as LLVM did prior
to this commit. As someone who has been looking at a lot of gcc vs clang
diffs lately, reducing unnecessary divergence is of at least some value.
* As the diff for fold-mem-offset.ll shows, we can fold memory offsets
in more cases when addi is used. Memory offset folding could be taught
to recognise when the addiw could be replaced with an addi, but that
seems unnecessary when we can simply change the logic in RISCVMatInt.
As pointed out by @topperc during review, making this change without
modifying RISCVOptWInstrs risks introducing some cases where we fail to
remove a sext.w that we removed before. I've incorporated a patch based
on a suggestion from Craig that avoids it, and also adds appropriate
RISCVOptWInstrs test cases.
The initial patch description noted that the main motivation was to
avoid unnecessary differences both for RV32/RV64 and when comparing GCC,
but noted that very occasionally we see a benefit from memory offset
folding kicking in when it didn't before. Looking at the dynamic
instruction count difference for SPEC benchmarks targeting rva22u64 and
it shows we actually get a meaningful
~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data
more closely, the codegen difference is in `LBM_performStreamCollideTRT`
which as a function accounts for ~98% for dynamically executed
instructions and the codegen diffs appear to be a knock-on effect of the
address merging reducing register pressure right from function entry
(for instance, we get a big reduction in dynamically executed loads in
that function).
Below is the icount data (rva22u64 -O3, no LTO):
```
Benchmark Baseline This PR Diff (%)
============================================================
500.perlbench_r 174116601991 174115795810 -0.00%
502.gcc_r 218903280858 218903215788 -0.00%
505.mcf_r 131208029185 131207692803 -0.00%
508.namd_r 217497594322 217497594297 -0.00%
510.parest_r 289314486153 289313577652 -0.00%
511.povray_r 30640531048 30640765701 0.00%
519.lbm_r 95897914862 91712688050 -4.36%
520.omnetpp_r 134641549722 134867015683 0.17%
523.xalancbmk_r 281462762992 281432092673 -0.01%
525.x264_r 379776121941 379535558210 -0.06%
526.blender_r 659736022025 659738387343 0.00%
531.deepsjeng_r 349122867552 349122867481 -0.00%
538.imagick_r 238558760552 238558753269 -0.00%
541.leela_r 406578560612 406385135260 -0.05%
544.nab_r 400997131674 400996765827 -0.00%
557.xz_r 130079522194 129945515709 -0.10%
```
The instcounting setup I use doesn't have good support for drilling down
into functions from outside the linked executable (e.g. libc). The
difference in omnetpp all seems to come from there, and does not reflect
any degradation in codegen quality.
I can confirm with the current version of the PR there is no change in
the number of static sext.w across all the SPEC 2017 benchmarks
(rva22u64 O3)
Co-authored-by: Craig Topper <craig.topper at sifive.com>
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list