[all-commits] [llvm/llvm-project] c4806d: [RISCV] Fold LI 1 / SLLI into BSETI during i64 mat...

Mon Jun 2 13:23:35 PDT 2025

  Branch: refs/heads/users/vitalybuka/spr/main.nfcipromotemem2reg-dont-handle-the-first-successor-out-of-order
  Home:   https://github.com/llvm/llvm-project
  Commit: c4806dbda348556d58fa10fa06b1d9dd95bac4c8
      https://github.com/llvm/llvm-project/commit/c4806dbda348556d58fa10fa06b1d9dd95bac4c8
  Author: Piotr Fusik <p.fusik at samsung.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll

  Log Message:
  -----------
  [RISCV] Fold LI 1 / SLLI into BSETI during i64 materialization (#142348)

My first approach was to avoid emitting LI 1 / SLLI in the first place.
Unfortunately, that favors BSETI C / ADDI -1 over LI -1 / SRLI 64-C
even though the latter has both instructions compressible.
This is because the code assumes in several places that
a two-instruction sequence (here: BSETI / ADDI) cannot be improved.

Another possible approach would be to keep LI 1 / SLLI if it is to be
later replaced with SRLI. This would be harder to grasp than eventually
patching LI 1 / SLLI with BSETI.

  Commit: 18e51314c41ea3093f28659cd15095778dfe88f7
      https://github.com/llvm/llvm-project/commit/18e51314c41ea3093f28659cd15095778dfe88f7
  Author: Amir Ayupov <aaupov at fb.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M bolt/include/bolt/Profile/DataAggregator.h
    M bolt/lib/Profile/DataAggregator.cpp
    A bolt/test/X86/Inputs/pre-aggregated-basic.txt
    M bolt/test/X86/pre-aggregated-perf.test
    M bolt/test/link_fdata.py

  Log Message:
  -----------
  [BOLT] Support pre-aggregated basic sample profile (#140196)

Define a pre-aggregated basic sample format:
```
E <event name>
S <location> <count>
```

`-nl` flag is required to use parsed basic samples.

Test Plan: update pre-aggregated-perf.test

  Commit: 0210750d5a5b4cfc8d2b6a9e94ace24d31d65ddc
      https://github.com/llvm/llvm-project/commit/0210750d5a5b4cfc8d2b6a9e94ace24d31d65ddc
  Author: Chao Chen <chao.chen at intel.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
    M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
    M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
    M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
    A mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
    M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
    M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
    A mlir/test/Dialect/XeGPU/xegpu-blocking.mlir

  Log Message:
  -----------
  [MLIR][XeGPU] Add unroll patterns and blocking pass for XeGPU [2/N] (#140163)

This PR introduces the initial implementation of a blocking pass for
XeGPU programs. The pass leverages unroll patterns from both the XeGPU
and Vector dialects. 

---------

Co-authored-by: Adam Siemieniuk <adam.siemieniuk at intel.com>

  Commit: 890f8729a240f3e3ae5605b6d997624ad45f1ac6
      https://github.com/llvm/llvm-project/commit/890f8729a240f3e3ae5605b6d997624ad45f1ac6
  Author: Jesse Huang <jesse.huang at sifive.com>
  Date:   2025-06-03 (Tue, 03 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/test/CodeGen/RISCV/nest-register.ll

  Log Message:
  -----------
  [RISCV] Use t3 for static chain register when branch CFI is enabled (#142344)

Use t3 for static chain register when branch CFI is enabled to align
with gcc.[1]

[1]
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.h#L417

  Commit: 4e9794fdbe266ce8e473c97f7ddc7b604780e5a0
      https://github.com/llvm/llvm-project/commit/4e9794fdbe266ce8e473c97f7ddc7b604780e5a0
  Author: Jesse Huang <jesse.huang at sifive.com>
  Date:   2025-06-03 (Tue, 03 Jun 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64-trampoline.ll

  Log Message:
  -----------
  [NFC][RISCV] Use -O0 in trampoline test for easier code observation (#142332)

A portion of the trampoline code is optimized into a load from the
constant pool, making the lit test unable to capture the value of it.
Disabling the optimization can keep them load from immediates and able
to observe any value changes.

  Commit: c005df3c7e7f8bf788803a95e27d57b339c965fe
      https://github.com/llvm/llvm-project/commit/c005df3c7e7f8bf788803a95e27d57b339c965fe
  Author: Ian Wood <ianwood2024 at u.northwestern.edu>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
    M mlir/test/Dialect/Linalg/canonicalize.mlir

  Log Message:
  -----------
  [mlir][linalg] Fix EraseIdentityLinalgOp on fill-like ops (#130000)

Adds a check to make sure that the linalg op is safe to erase by
ensuring that the `linalg.yield` is yielding one of the linalg op's
block args. This check already exists for linalg ops with pure tensor
semantics.

Closes https://github.com/llvm/llvm-project/issues/129414

---------

Signed-off-by: Ian Wood <ianwood2024 at u.northwestern.edu>

  Commit: eb9ed93fce4ac3726af0449ac5cee7cb829d3931
      https://github.com/llvm/llvm-project/commit/eb9ed93fce4ac3726af0449ac5cee7cb829d3931
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M offload/plugins-nextgen/common/src/Utils/ELF.cpp

  Log Message:
  -----------
  [Offload] Optimistically accept SM architectures (#142399)

Summary:
We try to clamp these to ones known to work, but we should probably just
optimistically accept these. I'd prefer to update the flag check, but
since NVIDIA refuses to publish their ELF format it's too much effort to
reverse engineer.

Fixes: https://github.com/llvm/llvm-project/issues/138532

  Commit: 06f13f868490adb075b4fbe2edd1432723ba7cdc
      https://github.com/llvm/llvm-project/commit/06f13f868490adb075b4fbe2edd1432723ba7cdc
  Author: Maksim Panchenko <maks at fb.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    A bolt/test/AArch64/patch-ignored.s
    A bolt/test/X86/patch-ignored.s

  Log Message:
  -----------
  [BOLT] Fix references in ignored functions in CFG state (#140678)

When we call setIgnored() on functions that already have CFG built,
these functions are not going to get emitted and we risk missing
external function references being updated.

To mitigate the potential issues, run scanExternalRefs() on such
functions to create patches/relocations.

Since scanExternalRefs() relies on function relocations, we have to
preserve relocations until the function is emitted. As a result, the
memory overhead without debug info update could reach up to 2%.

  Commit: f99e76b004bd1e5eb4fe42b22e0740df22e8881c
      https://github.com/llvm/llvm-project/commit/f99e76b004bd1e5eb4fe42b22e0740df22e8881c
  Author: Benjamin Kramer <benny.kra at googlemail.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [bazel] Port 0210750d5a5b4cfc8d2b6a9e94ace24d31d65ddc

  Commit: b88dfb0b23d0a1863414fb9450ee444766bfe7c9
      https://github.com/llvm/llvm-project/commit/b88dfb0b23d0a1863414fb9450ee444766bfe7c9
  Author: Chao Chen <chao.chen at intel.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
    M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
    M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
    M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
    R mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
    M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
    M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
    R mlir/test/Dialect/XeGPU/xegpu-blocking.mlir

  Log Message:
  -----------
  Revert "[MLIR][XeGPU] Add unroll patterns and blocking pass for XeGPU [2/N]" (#142459)

Reverts llvm/llvm-project#140163

  Commit: 66094a68f04b791856978755c655cb45befc8b84
      https://github.com/llvm/llvm-project/commit/66094a68f04b791856978755c655cb45befc8b84
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/include/bolt/Profile/DataAggregator.h
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Profile/DataAggregator.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    A bolt/test/AArch64/patch-ignored.s
    A bolt/test/X86/Inputs/pre-aggregated-basic.txt
    A bolt/test/X86/patch-ignored.s
    M bolt/test/X86/pre-aggregated-perf.test
    M bolt/test/link_fdata.py
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/nest-register.ll
    M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
    M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
    M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
    M mlir/test/Dialect/Linalg/canonicalize.mlir
    M offload/plugins-nextgen/common/src/Utils/ELF.cpp
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]

Compare: https://github.com/llvm/llvm-project/compare/a56a52922e9c...66094a68f04b

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