[all-commits] [llvm/llvm-project] 890f87: [RISCV] Use t3 for static chain register when bran...

[Jesse Huang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 890f8729a240f3e3ae5605b6d997624ad45f1ac6
      https://github.com/llvm/llvm-project/commit/890f8729a240f3e3ae5605b6d997624ad45f1ac6
  Author: Jesse Huang <jesse.huang at sifive.com>
  Date:   2025-06-03 (Tue, 03 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/test/CodeGen/RISCV/nest-register.ll

  Log Message:
  -----------
  [RISCV] Use t3 for static chain register when branch CFI is enabled (#142344)

Use t3 for static chain register when branch CFI is enabled to align
with gcc.[1]

[1]
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.h#L417



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