[all-commits] [llvm/llvm-project] c4806d: [RISCV] Fold LI 1 / SLLI into BSETI during i64 mat...

[Piotr Fusik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4806dbda348556d58fa10fa06b1d9dd95bac4c8
      https://github.com/llvm/llvm-project/commit/c4806dbda348556d58fa10fa06b1d9dd95bac4c8
  Author: Piotr Fusik <p.fusik at samsung.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll

  Log Message:
  -----------
  [RISCV] Fold LI 1 / SLLI into BSETI during i64 materialization (#142348)

My first approach was to avoid emitting LI 1 / SLLI in the first place.
Unfortunately, that favors BSETI C / ADDI -1 over LI -1 / SRLI 64-C
even though the latter has both instructions compressible.
This is because the code assumes in several places that
a two-instruction sequence (here: BSETI / ADDI) cannot be improved.

Another possible approach would be to keep LI 1 / SLLI if it is to be
later replaced with SRLI. This would be harder to grasp than eventually
patching LI 1 / SLLI with BSETI.



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