[all-commits] [llvm/llvm-project] 05eef6: IR/Verifier: Allow vector type in atomic load and ...

[jofrn via All-commits]

  Branch: refs/heads/users/jofrn/gt/atomicvec-stack4
  Home:   https://github.com/llvm/llvm-project
  Commit: 05eef63446c0dda7eb61c2ba57de41a877e42d0c
      https://github.com/llvm/llvm-project/commit/05eef63446c0dda7eb61c2ba57de41a877e42d0c
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/IR/Verifier.cpp
    M llvm/test/Assembler/atomic.ll
    M llvm/test/Verifier/atomics.ll

  Log Message:
  -----------
  IR/Verifier: Allow vector type in atomic load and store

Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.

commit-id:72529270


  Commit: d711f83da19661bbf8fae2ef0ad64bd1bb834e44
      https://github.com/llvm/llvm-project/commit/d711f83da19661bbf8fae2ef0ad64bd1bb834e44
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [SelectionDAG] Legalize <1 x T> vector types for atomic load

`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.

commit-id:5c36cc8c


  Commit: c6adf851f514295e15f7cca1cc63fb75a84ae32d
      https://github.com/llvm/llvm-project/commit/c6adf851f514295e15f7cca1cc63fb75a84ae32d
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [X86] Manage atomic load of fp -> int promotion in DAG

When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.

commit-id:f9d761c5


  Commit: 3364982a3c7de07b8b2e42cf9463acb71562cbd1
      https://github.com/llvm/llvm-project/commit/3364982a3c7de07b8b2e42cf9463acb71562cbd1
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [X86] Add atomic vector tests for unaligned >1 sizes.

Unaligned atomic vectors with size >1 are lowered to calls.
Adding their tests separately here.

commit-id:a06a5cc6


  Commit: 38e98d8ba2b8bfff0a9019683c4386b1e0637bf8
      https://github.com/llvm/llvm-project/commit/38e98d8ba2b8bfff0a9019683c4386b1e0637bf8
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [SelectionDAG] Widen <2 x T> vector types for atomic load

Vector types of 2 elements must be widened. This change does this
for vector types of atomic load in SelectionDAG
so that it can translate aligned vectors of >1 size.

commit-id:2894ccd1


  Commit: 74d77f7a3b33834127223bb61df2697ba9ef88d8
      https://github.com/llvm/llvm-project/commit/74d77f7a3b33834127223bb61df2697ba9ef88d8
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [X86] Remove extra MOV after widening atomic load

This change adds patterns to optimize out an extra MOV
present after widening the atomic load.

commit-id:45989503


  Commit: ef31affba0d85387f26e6595e0c0266235166ef4
      https://github.com/llvm/llvm-project/commit/ef31affba0d85387f26e6595e0c0266235166ef4
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/CodeGen/X86/atomic-load-store.ll

  Log Message:
  -----------
  [X86] Cast atomic vectors in IR to support floats

This commit casts floats to ints in an atomic load during AtomicExpand to support
floating point types. It also is required to support 128 bit vectors in SSE/AVX.

commit-id:80b9b6a7


  Commit: 9c36e73fa40bcadd31dbb76d1b7d0a4ab42549f6
      https://github.com/llvm/llvm-project/commit/9c36e73fa40bcadd31dbb76d1b7d0a4ab42549f6
  Author: jofrn <jofernau at amd.com>
  Date:   2025-06-02 (Mon, 02 Jun 2025)

  Changed paths:
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/test/CodeGen/ARM/atomic-load-store.ll
    M llvm/test/CodeGen/X86/atomic-load-store.ll
    M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll

  Log Message:
  -----------
  [AtomicExpand] Add bitcasts when expanding load atomic vector

AtomicExpand fails for aligned `load atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
bitcasts so that the call can be lowered. It also adds support for
128 bit lowering in tablegen to support SSE/AVX.

commit-id:f430c1af


Compare: https://github.com/llvm/llvm-project/compare/05eef63446c0%5E...9c36e73fa40b

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