[all-commits] [llvm/llvm-project] d11f9d: AMDGPU: Avoid using kernels in f16 copysign test (...

Fri May 30 13:07:01 PDT 2025

  Branch: refs/heads/users/kparzysz/spr/a04-atomic-one
  Home:   https://github.com/llvm/llvm-project
  Commit: d11f9d45e4fa872598e5ce61390d53c7901fdebf
      https://github.com/llvm/llvm-project/commit/d11f9d45e4fa872598e5ce61390d53c7901fdebf
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

  Log Message:
  -----------
  AMDGPU: Avoid using kernels in f16 copysign test (#142113)

Avoid the memory noise in tests that predate function support.

  Commit: c9cca5cdc407390f3faf9025eb62720d7b293960
      https://github.com/llvm/llvm-project/commit/c9cca5cdc407390f3faf9025eb62720d7b293960
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    A llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll

  Log Message:
  -----------
  AMDGPU: Move bf16 copysign tests to separate file (#142114)

Make symmetric with other copysign tests

  Commit: ba4f4a1a181590d532a760a5e3dd233aeadd4267
      https://github.com/llvm/llvm-project/commit/ba4f4a1a181590d532a760a5e3dd233aeadd4267
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

  Log Message:
  -----------
  AMDGPU: Add more f16 copysign tests (#142115)

  Commit: e39e99022a4bc3ed9bcafd25a28a7a4ad23832fb
      https://github.com/llvm/llvm-project/commit/e39e99022a4bc3ed9bcafd25a28a7a4ad23832fb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

  Log Message:
  -----------
  AMDGPU: Handle vectors in copysign magnitude sign case (#142156)

  Commit: 6a6aec6f4ed014bd11daf1cf29e225b43466b239
      https://github.com/llvm/llvm-project/commit/6a6aec6f4ed014bd11daf1cf29e225b43466b239
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

  Log Message:
  -----------
  AMDGPU: Handle vectors in copysign sign type combine (#142157)

This avoids some ugly codegen on pre-16-bit instruction targets now
from annoying f16 legalization effects. This also avoids regressions
on newer targets in a future patch.

  Commit: 443cdd0b48b850b9f2d7cb93f9cc0ba8d5ac4827
      https://github.com/llvm/llvm-project/commit/443cdd0b48b850b9f2d7cb93f9cc0ba8d5ac4827
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
    M llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll

  Log Message:
  -----------
  [RISCV] Fix a bug in partial.reduce lowering for zvqdotq .vx forms (#142185)

I'd missed a bitcast in the lowering. Unfortunately, that bitcast
happens to be semantically required here as the partial_reduce_* source
expects an i8 element type, but the pseudos and patterns expect an i32
element type.

This appears to only influence the .vx matching from the cases I've
found so far, and LV does not yet generate anything which will exercise
this. The reduce path (instead of the partial.reduce one) used by SLP
currently manually constructs the i32 value, and then goes directly to
the pseudo's with their i32 arguments, not the partial_reduce nodes.

We're basically loosing the .vx matching on this path until we teach
splat matching to be able to manually splat the i8 value into an i32 via
LUI/ADDI.

  Commit: 8eb4ada181dc80e1c31c30c02e0bed6ca415047b
      https://github.com/llvm/llvm-project/commit/8eb4ada181dc80e1c31c30c02e0bed6ca415047b
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll

  Log Message:
  -----------
  [RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available (#142036)

If we have the ri.vinsert/vextract instructions from xrivosvisni, we can
do an element insert or extract without needing a vslide or a vector
temporary register. Adjust the TTI cost to reflect this.

  Commit: 4dcfcd3a66847e2ed377efdefa22fea9b59a8285
      https://github.com/llvm/llvm-project/commit/4dcfcd3a66847e2ed377efdefa22fea9b59a8285
  Author: Amr Hesham <amr96 at programmer.net>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
    M clang/test/CIR/CodeGen/vector-ext.cpp
    M clang/test/CIR/CodeGen/vector.cpp
    A clang/test/CIR/IR/invalid-vector-shuffle-dyn-wrong-operands.cir
    M clang/test/CIR/IR/vector.cir

  Log Message:
  -----------
  [CIR] Upstream ShuffleDynamicOp for VectorType (#141411)

This change adds support for the Dynamic Shuffle op for VectorType

Issue https://github.com/llvm/llvm-project/issues/136487

  Commit: 46b389218bf392b87fe9d375e4214a6faf470ec5
      https://github.com/llvm/llvm-project/commit/46b389218bf392b87fe9d375e4214a6faf470ec5
  Author: Folkert de Vries <flokkievids at gmail.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/test/CodeGen/ARM/arm32-rounding.ll
    M llvm/test/CodeGen/ARM/fp16-fullfp16.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/vrint.ll
    M llvm/test/CodeGen/Thumb2/bf16-instructions.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll

  Log Message:
  -----------
  [ARM]: codegen `llvm.roundeven.v*` (#141786)

fixes https://github.com/llvm/llvm-project/issues/73588

The aarch64 version of `frintn.ll` notes the intention to auto-upgrade
`frintn` to `roundeven`. I haven't been able to figure out how to make
that happen though (either for arm or aarch64).

The original issue came up in
https://github.com/rust-lang/stdarch/pull/1807

  Commit: f7e172da4caeab9d92f6e97501b1a2c561e616c1
      https://github.com/llvm/llvm-project/commit/f7e172da4caeab9d92f6e97501b1a2c561e616c1
  Author: Michael Buch <michaelbuch12 at gmail.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M libcxxabi/src/demangle/cp-to-llvm.sh
    A libcxxabi/test/DemangleTestCases.inc
    M libcxxabi/test/test_demangle.pass.cpp
    A llvm/include/llvm/Testing/Demangle/DemangleTestCases.inc
    A llvm/include/llvm/Testing/Demangle/README.txt

  Log Message:
  -----------
  [ItaniumDemangle][test] Factor demangler test-cases into file and sync into LLVM (#137947)

This patch turns the `libcxxabi/test/test_demangle.pass.cpp` into gtest
unit-tests in `llvm/unittests/Demangle`. The main motivation for this is
https://github.com/llvm/llvm-project/pull/137793, where we want to
re-use the test-cases from the ItaniumDemangler to test our OutputBuffer
implementation.

`libcxxabi/test/test_demangle.pass.cpp` now only tests the
`__cxa_demangle` API surface, not the underlying ItaniumDemangle
implementation.

  Commit: c5f3018668efea156831feb24843e34e4602a8e6
      https://github.com/llvm/llvm-project/commit/c5f3018668efea156831feb24843e34e4602a8e6
  Author: Aviad Cohen <aviadcohen7 at gmail.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M mlir/include/mlir/IR/OperationSupport.h
    M mlir/lib/IR/OperationSupport.cpp
    M mlir/unittests/IR/OperationSupportTest.cpp

  Log Message:
  -----------
  [mlir]: Added properties/attributes ignore flags to OperationEquivalence (#141664)

Those flags are useful for cases and operation which we may consider
equivalent even when their attributes/properties are not the same.

  Commit: 9e9626b3d5aa56828b71b03d99bf3167fdfeb08d
      https://github.com/llvm/llvm-project/commit/9e9626b3d5aa56828b71b03d99bf3167fdfeb08d
  Author: nerix <nerixdev at outlook.de>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
    M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
    A lldb/test/Shell/Process/Windows/msstl_smoke.cpp

  Log Message:
  -----------
  [LLDB] Avoid crashes when inspecting MSVC STL types (#140761)

When inspecting/printing types from MSVC's STL, LLDB would crash because
it assumes these types were from libstdc++. Specifically,
`std::shared_ptr` and `std::optional` would crash because of a null
pointer dereference. I added a minimal test that tests the types with
C++ helpers for libstdc++ (only tests for crashes).

- Fixes #115216 
- Fixes #120310 

This still has one unresolved discussion: What about MS STL types? This
is https://github.com/llvm/llvm-project/issues/24834, but there was a
bit of discussion in #120310 as well. The main issue is that MSVC's STL
uses the same type names as libstdc++ (i.e. neither uses an inline
namespace like libc++ for some types).

  Commit: 03d1f3d7e34d3420b8ddafa7e6df0c1d8ad13c41
      https://github.com/llvm/llvm-project/commit/03d1f3d7e34d3420b8ddafa7e6df0c1d8ad13c41
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M lldb/include/lldb/Expression/DiagnosticManager.h
    M lldb/include/lldb/Symbol/VariableList.h

  Log Message:
  -----------
  [lldb][nfc] Fix missing move operations and constness of methods (#142052)

This PR adds the missing move operators for VariableList: this class is
just a wrapper around a vector, so it can use the default move
operations. Subsequent patches will want to return VariableLists from
functions, so the move operation is required (the copy constructors are
deleted).

It also fixes constness for a method in DiagnosticManager returning its
list of diagnostics. Previously, the method always returned a const
list, even though the method was not const itself. Subsequent patches
will make use of the ability to mutate the diagnostics.

  Commit: d4791f56f31e54d66e606e783ba21b99346caf7c
      https://github.com/llvm/llvm-project/commit/d4791f56f31e54d66e606e783ba21b99346caf7c
  Author: sribee8 <145801438+sribee8 at users.noreply.github.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M libc/config/linux/x86_64/entrypoints.txt
    M libc/include/wchar.yaml
    M libc/src/wchar/CMakeLists.txt
    A libc/src/wchar/wcsspn.cpp
    A libc/src/wchar/wcsspn.h
    M libc/test/src/wchar/CMakeLists.txt
    A libc/test/src/wchar/wcsspn_test.cpp

  Log Message:
  -----------
  [libc] wcsspn implementation (#142034)

Implemented wcsspn as well as tests for the function.

---------

Co-authored-by: Sriya Pratipati <sriyap at google.com>

  Commit: 4d7e6227269326318de9c0920ccb1e8fa632a51c
      https://github.com/llvm/llvm-project/commit/4d7e6227269326318de9c0920ccb1e8fa632a51c
  Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
    M clang/test/CIR/CodeGen/vector-ext.cpp
    M clang/test/CIR/CodeGen/vector.cpp
    A clang/test/CIR/IR/invalid-vector-shuffle-dyn-wrong-operands.cir
    M clang/test/CIR/IR/vector.cir
    M libc/config/linux/x86_64/entrypoints.txt
    M libc/include/wchar.yaml
    M libc/src/wchar/CMakeLists.txt
    A libc/src/wchar/wcsspn.cpp
    A libc/src/wchar/wcsspn.h
    M libc/test/src/wchar/CMakeLists.txt
    A libc/test/src/wchar/wcsspn_test.cpp
    M libcxxabi/src/demangle/cp-to-llvm.sh
    A libcxxabi/test/DemangleTestCases.inc
    M libcxxabi/test/test_demangle.pass.cpp
    M lldb/include/lldb/Expression/DiagnosticManager.h
    M lldb/include/lldb/Symbol/VariableList.h
    M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
    M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
    A lldb/test/Shell/Process/Windows/msstl_smoke.cpp
    A llvm/include/llvm/Testing/Demangle/DemangleTestCases.inc
    A llvm/include/llvm/Testing/Demangle/README.txt
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
    A llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/ARM/arm32-rounding.ll
    M llvm/test/CodeGen/ARM/fp16-fullfp16.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/vrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
    M llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
    M llvm/test/CodeGen/Thumb2/bf16-instructions.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
    M llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll
    M mlir/include/mlir/IR/OperationSupport.h
    M mlir/lib/IR/OperationSupport.cpp
    M mlir/unittests/IR/OperationSupportTest.cpp

  Log Message:
  -----------
  Merge branch 'main' into users/kparzysz/spr/a04-atomic-one

Compare: https://github.com/llvm/llvm-project/compare/f7bc109276a7...4d7e62272693

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