[all-commits] [llvm/llvm-project] 443cdd: [RISCV] Fix a bug in partial.reduce lowering for z...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 443cdd0b48b850b9f2d7cb93f9cc0ba8d5ac4827
      https://github.com/llvm/llvm-project/commit/443cdd0b48b850b9f2d7cb93f9cc0ba8d5ac4827
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
    M llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll

  Log Message:
  -----------
  [RISCV] Fix a bug in partial.reduce lowering for zvqdotq .vx forms (#142185)

I'd missed a bitcast in the lowering. Unfortunately, that bitcast
happens to be semantically required here as the partial_reduce_* source
expects an i8 element type, but the pseudos and patterns expect an i32
element type.

This appears to only influence the .vx matching from the cases I've
found so far, and LV does not yet generate anything which will exercise
this. The reduce path (instead of the partial.reduce one) used by SLP
currently manually constructs the i32 value, and then goes directly to
the pseudo's with their i32 arguments, not the partial_reduce nodes.

We're basically loosing the .vx matching on this path until we teach
splat matching to be able to manually splat the i8 value into an i32 via
LUI/ADDI.



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