[all-commits] [llvm/llvm-project] 548319: [RISCV] Add shlcofideleg extension (#141572)

[Ying Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5483190216cb0ff3b9f0e1a3ca901ad1b259ba82
      https://github.com/llvm/llvm-project/commit/5483190216cb0ff3b9f0e1a3ca901ad1b259ba82
  Author: Ying Chen <chenying at inchitech.com>
  Date:   2025-05-30 (Fri, 30 May 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add shlcofideleg extension (#141572)

This is for `shlcofideleg` extension, that supports delegating LCOFI
interrupts to VS-mode.

Spec:
https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc



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