[all-commits] [llvm/llvm-project] 84a69a: [AMDGPU] Move InferAddressSpacesPass to middle end...

[Shilei Tian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84a69a0f8f60b6d852b9a16be199bfa432706b0c
      https://github.com/llvm/llvm-project/commit/84a69a0f8f60b6d852b9a16be199bfa432706b0c
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2025-05-29 (Thu, 29 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/swdev282079.ll
    M llvm/test/CodeGen/AMDGPU/uniform_branch_with_floating_point_cond.ll
    A llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll
    A llvm/test/Transforms/PhaseOrdering/AMDGPU/infer-address-space.ll
    A llvm/test/Transforms/PhaseOrdering/AMDGPU/lit.local.cfg

  Log Message:
  -----------
  [AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604)

It will run twice in the non-LTO pipeline with `O1` or higher. In LTO post link pipeline, it will be run once with `O2` or higher, since inline and SROA don't run in `O1`.



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