[all-commits] [llvm/llvm-project] dce490: [RISCV] Custom type legalize MVT::i8 BITREVERSE to...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dce490e529ead7885852950394d520de1f53b917
      https://github.com/llvm/llvm-project/commit/dce490e529ead7885852950394d520de1f53b917
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-29 (Thu, 29 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

  Log Message:
  -----------
  [RISCV] Custom type legalize MVT::i8 BITREVERSE to BREV8. (#142001)

If we're only reversing a single byte, we can use BREV8 directly.

If we let it type legalize we'll get (srl (bitreverse X), XLen-8). In op
legalization, we'll expand that to (srl (brev8 (bswap X)), XLen - 8).
Then, SimplifyDemandedBits can reduce it to (srl (brev8 (shl X, XLen -
8)), XLen - 8). We could add a DAGCombine to pull the shl through the
brev8 to put it next to the srl which will allow it to become (and
(brev8 X), 255). Unless we can prove the upper XLen-8 bits are 0 or that
they aren't demanded, we can't remove the `and`.

By emitting BREV8 directly when we still know the type is i8, we can
avoid this. We already DAGCombine i16 and i32 (bitreverse (bswap X)) to
BREV8 early for the same reason.

I've added an i7 test case so we can still see the opportunity for
improvement on weird sizes.

Fixes the RISC-V part of #141863.



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