[all-commits] [llvm/llvm-project] 16994a: [RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 16994a6e768658221c69c85c1b8ecf4225d875c9
      https://github.com/llvm/llvm-project/commit/16994a6e768658221c69c85c1b8ecf4225d875c9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-05-29 (Thu, 29 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

  Log Message:
  -----------
  [RISCV] Add a PseudoVSETVLIX0X0 pseudo for the x0,x0 vsetvli. NFC (#141875)

Strengthen the register class on PseudoVSETVLIX0 to disallow X0 as a
destination. This allows removal of an opcode check from
RISCVDeadRegisterDefinitions. Now the register class will prevent the
conversion to X0.

I'm considering removing the explicit X0 operands and adding them during
PseudoExpansion, but it complicates finding the vtype operand.



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