[all-commits] [llvm/llvm-project] a7322d: [Xtensa] Implement Xtensa Region Protection Option...

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a7322d7948637aa45e9d86162601a97eb0ac2668
      https://github.com/llvm/llvm-project/commit/a7322d7948637aa45e9d86162601a97eb0ac2668
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2025-05-29 (Thu, 29 May 2025)

  Changed paths:
    M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    A llvm/test/MC/Disassembler/Xtensa/clamps.txt
    M llvm/test/MC/Disassembler/Xtensa/code_density.txt
    A llvm/test/MC/Disassembler/Xtensa/dcache.txt
    A llvm/test/MC/Disassembler/Xtensa/div.txt
    A llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt
    A llvm/test/MC/Disassembler/Xtensa/loop.txt
    A llvm/test/MC/Disassembler/Xtensa/mac16.txt
    A llvm/test/MC/Disassembler/Xtensa/minmax.txt
    A llvm/test/MC/Disassembler/Xtensa/miscsr.txt
    A llvm/test/MC/Disassembler/Xtensa/mul.txt
    A llvm/test/MC/Disassembler/Xtensa/mul16.txt
    A llvm/test/MC/Disassembler/Xtensa/mul32high.txt
    A llvm/test/MC/Disassembler/Xtensa/nsa.txt
    A llvm/test/MC/Disassembler/Xtensa/region_protect.txt
    A llvm/test/MC/Disassembler/Xtensa/rvector.txt
    A llvm/test/MC/Disassembler/Xtensa/sext.txt
    A llvm/test/MC/Xtensa/clamps-invalid.s
    A llvm/test/MC/Xtensa/clamps.s
    A llvm/test/MC/Xtensa/dcache.s
    A llvm/test/MC/Xtensa/extendedl32r.s
    A llvm/test/MC/Xtensa/miscsr.s
    A llvm/test/MC/Xtensa/region_protect.s
    A llvm/test/MC/Xtensa/rvector.s
    M llvm/test/MC/Xtensa/xtensa-mac16.s

  Log Message:
  -----------
  [Xtensa] Implement Xtensa Region Protection Option and several other small Options. (#137135)

Implement support of the Xtensa Region Protection, Extended L32R, Data
Cache, Relocatable Vector and MISC Special Registers Options.



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