[all-commits] [llvm/llvm-project] cfece5: [clang][ASTMatchers][NFC] fix typos in AST-matcher...
Qinkun Bao via All-commits
all-commits at lists.llvm.org
Wed May 28 07:35:05 PDT 2025
Branch: refs/heads/users/qinkunbao/spr/ubsan-support-srcsanitize-for-multiple-ignorelists
Home: https://github.com/llvm/llvm-project
Commit: cfece5abe34edf74bbdd23aea706fa3988c09db0
https://github.com/llvm/llvm-project/commit/cfece5abe34edf74bbdd23aea706fa3988c09db0
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/include/clang/ASTMatchers/ASTMatchFinder.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
Log Message:
-----------
[clang][ASTMatchers][NFC] fix typos in AST-matchers docs. (#141307)
Commit: 16bbfe1d0a3fcbb3cfb01fbec3a89f2d64a96549
https://github.com/llvm/llvm-project/commit/16bbfe1d0a3fcbb3cfb01fbec3a89f2d64a96549
Author: John Harrison <harjohn at google.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
Log Message:
-----------
[lldb] Correcting an error message. (#141696)
'isconnect' I assume was supposed to be 'disconnect'.
Commit: 7c471e12c80f86ba089fb5951ece4d516996d9a1
https://github.com/llvm/llvm-project/commit/7c471e12c80f86ba089fb5951ece4d516996d9a1
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M lldb/test/API/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py
Log Message:
-----------
[lldb][NFC] This test is marked expectedfail for macos version
less-than-14.4. Our CI bot is running macOS 14.1 but I still see
FAILs from this text in the CI logs? It may be that the CI is
really seeing TestTemplateWithSameArg.py fail and is highlighting
this XFAIL test even though it's expected. But I'm not interested
enough, I'll try just skipping it altogether on < macOS 14.4. This
does mean I'm skipping it on intel where the kernel never had the
issue involved.
Commit: 0b75a2099041bbd1155d93528bce98254f6f47b2
https://github.com/llvm/llvm-project/commit/0b75a2099041bbd1155d93528bce98254f6f47b2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
Log Message:
-----------
[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
Commit: 11b5e29cb4b4559f6e64302c089d9048f3c2624d
https://github.com/llvm/llvm-project/commit/11b5e29cb4b4559f6e64302c089d9048f3c2624d
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqcilb-valid.s
M llvm/test/MC/RISCV/xqcili-valid.s
Log Message:
-----------
[RISCV] Add compress patterns for QC_E_J/JAL and QC_E_LI (#141561)
Commit: 5c063bebe410b7ff803e377ab40d405db2956339
https://github.com/llvm/llvm-project/commit/5c063bebe410b7ff803e377ab40d405db2956339
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
Log Message:
-----------
[Clang] Fix a regression introduced by #138518 (#141342)
We did not handle the case where a variable could be initialized by a
CXXParenListInitExpr.
---------
Co-authored-by: Shafik Yaghmour <shafik.yaghmour at intel.com>
Commit: 3cd8924c31bc0d85617a4b6e686f702df242c7a2
https://github.com/llvm/llvm-project/commit/3cd8924c31bc0d85617a4b6e686f702df242c7a2
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc] Update serializer for improved template handling (#138065)
This patch updates Serialize.cpp to serialize more data about C++
templates, which are supported by the new mustache HTML template.
Split from #133161.
Co-authored-by: Peter Chou <peter.chou at mail.utoronto.ca>
Commit: 79023dbdb3ed682d134582f031848a24ce2931ba
https://github.com/llvm/llvm-project/commit/79023dbdb3ed682d134582f031848a24ce2931ba
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
A clang-tools-extra/test/clang-doc/basic-project.mustache.test
Log Message:
-----------
[clang-doc] Update clang-doc tool to enable mustache templates (#138066)
This patch adds a command line option and enables the Mustache template
HTML backend. This allows users to use the new, more flexible templates
over the old and cumbersome HTML output. Split from #133161.
Co-authored-by: Peter Chou <peter.chou at mail.utoronto.ca>
Commit: 1ad5783c07cf843fcb86c54b3cc158e0bc57f7af
https://github.com/llvm/llvm-project/commit/1ad5783c07cf843fcb86c54b3cc158e0bc57f7af
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
Log Message:
-----------
[clang-doc] Track if a type is a template or builtin (#138067)
Originally part of #133161. This patch adds preliminary tracking
for of TypeInfo, by tracking if the type is a builtin or template.
The new functionality is not yet exercised.
Co-authored-by: Peter Chou <peter.chou at mail.utoronto.ca>
Commit: 27675ccdd6315b560f5f90db34f6a4520fa26b6b
https://github.com/llvm/llvm-project/commit/27675ccdd6315b560f5f90db34f6a4520fa26b6b
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
M clang/test/CodeGenHLSL/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resource-bindings.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceImplicitBinding.cpp
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll
M llvm/test/CodeGen/DirectX/BufferLoad.ll
M llvm/test/CodeGen/DirectX/BufferStore-errors.ll
M llvm/test/CodeGen/DirectX/BufferStore-sm61.ll
M llvm/test/CodeGen/DirectX/BufferStore.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/array-typedgep.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/arrays.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/scalars.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/vectors.ll
M llvm/test/CodeGen/DirectX/CBufferLoadLegacy-errors.ll
M llvm/test/CodeGen/DirectX/CBufferLoadLegacy.ll
M llvm/test/CodeGen/DirectX/ContainerData/PSVResources-order.ll
M llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/arrays.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/multiple-spaces.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/simple.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/unbounded-arrays-error.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/unbounded-arrays.ll
M llvm/test/CodeGen/DirectX/Metadata/cbuffer-only.ll
M llvm/test/CodeGen/DirectX/Metadata/cbuffer_metadata.ll
M llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll
M llvm/test/CodeGen/DirectX/Metadata/srv_metadata.ll
M llvm/test/CodeGen/DirectX/Metadata/uav_metadata.ll
M llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll
M llvm/test/CodeGen/DirectX/RawBufferLoad.ll
M llvm/test/CodeGen/DirectX/RawBufferStore-error64.ll
M llvm/test/CodeGen/DirectX/RawBufferStore.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/load_rawbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/store_rawbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.5.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/raw-and-structured-buffers.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-alias-0.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-alias-1.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-valver1.8.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.8.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-vs.ll
M llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
M llvm/test/CodeGen/DirectX/resource_counter_error.ll
M llvm/unittests/Target/DirectX/ResourceBindingAnalysisTests.cpp
M llvm/unittests/Target/DirectX/UniqueResourceFromUseTests.cpp
Log Message:
-----------
[DirectX] Add resource name argument to llvm.dx.handlefrom[implicit]binding intrinsics (#139991)
Adds resource name argument to `llvm.dx.handlefrombinding` and `llvm.dx.handlefromimplicitbinding` intrinsics.
SPIR-V currently does not seem to need the resource names so this change only affects DirectX binding intrinsics.
Part 2/4 of https://github.com/llvm/llvm-project/issues/105059
Commit: 74a102fc1cbcdc04d02b4edf9bbcbdc93124d5c1
https://github.com/llvm/llvm-project/commit/74a102fc1cbcdc04d02b4edf9bbcbdc93124d5c1
Author: Martin Storsjö <martin at martin.st>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp
Log Message:
-----------
[libcxx] [test] Change an MSVC mode XFAIL into UNSUPPORTED (#141609)
The underlying bug in vcruntime [1] has been fixed in the latest version
of MSVC (released two weeks ago); this will cause the test which is
currently marked XFAIL to start erroring, when it starts passing
unexpectedly.
This version of MSVC may soon start appearing in the Github Actions
runner images used for our CI.
We could try to detect the state of this bug, but in practice, such
detection code would essentially be a copy of this whole test.
Therefore, just mark this test UNSUPPORTED for the MSVC mode builds. If
we at some point require new enough MSVC libraries, we could remove the
marking entirely.
[1]
https://developercommunity.visualstudio.com/t/vcruntime-nothrow-array-operator-new-fal/10373274
Commit: 47c04c735acde68c72500e21b6ebd606b37064b3
https://github.com/llvm/llvm-project/commit/47c04c735acde68c72500e21b6ebd606b37064b3
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[TableGen] Remove wrong comment for CodeGenTarget ctor (#141024)
Commit: 3e47d8debad01801dcc2128001f2f1465c29b748
https://github.com/llvm/llvm-project/commit/3e47d8debad01801dcc2128001f2f1465c29b748
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AArch64/expand-select.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vec_umulo.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/PowerPC/p10-fi-elim.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/zilsd.ll
Log Message:
-----------
MachineScheduler: Reset next cluster candidate for each node (#139513)
When a node is picked, we should reset its next cluster candidate to
null before releasing its successors/predecessors.
Commit: f2cd146072589f8b096ff46d3468361a6a63e24e
https://github.com/llvm/llvm-project/commit/f2cd146072589f8b096ff46d3468361a6a63e24e
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Log Message:
-----------
[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)
Fix RISC-V Indirect Branch Tracking pass was not showing in the pass
debug output due to not initialized properly.
Commit: 042912fe0ab12f8841d16890ed1e1c2a869b880b
https://github.com/llvm/llvm-project/commit/042912fe0ab12f8841d16890ed1e1c2a869b880b
Author: Michele Scuttari <michele.scuttari at outlook.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
Log Message:
-----------
[MLIR] Document the need for updating the cached symbol tables during bufferization (#141594)
Commit: 452894207ae28cde9c22e2935df2d960fa7585a9
https://github.com/llvm/llvm-project/commit/452894207ae28cde9c22e2935df2d960fa7585a9
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/source/Core/AddressRange.cpp
M lldb/test/Shell/SymbolFile/Breakpad/stack-cfi-parsing.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-raSearch.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-stack-cfi.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-stack-win.test
M lldb/test/Shell/SymbolFile/target-symbols-add-unwind.test
M lldb/test/Shell/Unwind/basic-block-sections-with-dwarf-static.test
Log Message:
-----------
[lldb] Make AddressRange dump easier on the eye (#141062)
Commit: 8adcc8a669f093d6fe74645900515e4561102248
https://github.com/llvm/llvm-project/commit/8adcc8a669f093d6fe74645900515e4561102248
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Log Message:
-----------
[SelectionDAG] Introduce ISD::PTRADD (#140017)
This opcode represents the addition of a pointer value (first operand)
and an integer offset (second operand). PTRADD nodes are only generated
if the TargetMachine opts in by overriding
TargetMachine::shouldPreservePtrArith().
The PTRADD node and respective visitPTRADD() function were adapted by
@rgwott from the CHERI/Morello LLVM tree.
Original authors: @davidchisnall, @jrtc27, @arichardson.
The changes in this PR were extracted from PR #105669.
---------
Co-authored-by: David Chisnall <github at theravensnest.org>
Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>
Co-authored-by: Alexander Richardson <alexrichardson at google.com>
Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich at arm.com>
Commit: cbe2352c4dc607da71e7bd40213b8922fbdee482
https://github.com/llvm/llvm-project/commit/cbe2352c4dc607da71e7bd40213b8922fbdee482
Author: David Green <david.green at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/tbz-tbnz.ll
Log Message:
-----------
[AArch64][GlobalISel] Regenerate and add gisel coverage for tbz-tbnz.ll. NFC
Commit: a69487da2e746d747fc0dc19d416a7d654c8c148
https://github.com/llvm/llvm-project/commit/a69487da2e746d747fc0dc19d416a7d654c8c148
Author: Kazu Hirata <kazu at google.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[lldb] Fix warnings (#141687)
This patch fixes:
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4137:11:
error: enumeration value 'HLSLInlineSpirv' not handled in switch
[-Werror,-Wswitch]
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4844:11:
error: enumeration value 'HLSLInlineSpirv' not handled in switch
[-Werror,-Wswitch]
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:5142:11:
error: enumeration value 'HLSLInlineSpirv' not handled in switch
[-Werror,-Wswitch]
Commit: f8ca9e59cb438bd35b29a6d7cf6d72f50673aec9
https://github.com/llvm/llvm-project/commit/f8ca9e59cb438bd35b29a6d7cf6d72f50673aec9
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Object/OffloadBundle.cpp
Log Message:
-----------
[llvm][llvm-objdump] Fix fatbin handling on 32-bit systems (#141620)
Which fixes a test failure seen on the bots, introduced by
https://github.com/llvm/llvm-project/pull/140286.
```
[ RUN ] OffloadingBundleTest.checkExtractOffloadBundleFatBinary
ObjectTests: ../llvm/llvm/include/llvm/ADT/StringRef.h:618: StringRef llvm::StringRef::drop_front(size_t) const: Assertion `size() >= N && "Dropping more elements than exist"' failed.
0 0x0a24a990 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/tcwg-buildbot/worker/clang-armv8-quick/stage1/unittests/Object/./ObjectTests+0x31a990)
1 0x0a248364 llvm::sys::RunSignalHandlers() (/home/tcwg-buildbot/worker/clang-armv8-quick/stage1/unittests/Object/./ObjectTests+0x318364)
2 0x0a24b410 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
3 0xf46ed6f0 __default_rt_sa_restorer ./signal/../sysdeps/unix/sysv/linux/arm/sigrestorer.S:80:0
4 0xf46ddb06 ./csu/../sysdeps/unix/sysv/linux/arm/libc-do-syscall.S:47:0
5 0xf471d292 __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
6 0xf46ec840 gsignal ./signal/../sysdeps/posix/raise.c:27:6
```
Also reported on 32-bit x86.
I think the cause is the code was casting the result of StringRef.find
into an int64_t. The failure value of find is StringRef::npos, which is
defined as:
static constexpr size_t npos = ~size_t(0);
* size_t(0) is 32 bits of 0s
* the inverse of that is 32 bits of 1s
* Cast to int64_t needs to widen this, and it will preserve the original
value in doing so, which is 0xffffffff.
* The result is 0x00000000ffffffff, which is >= 0, so we keep searching
and try to go off the end of the file.
Or put another way, this equivalent function returns true when compiled
for a 32-bit system:
```
bool fn() {
size_t foo = ~size_t(0);
int64_t foo64 = (int64_t)foo;
return foo64 >= 0;
}
```
Using size_t throughout fixes the problem. Also I don't see a reason it
needs to be a signed number, given that it always searches forward from
the current offset.
Commit: a615975bd9fe413f17ee43b231912ef2e8ccbd64
https://github.com/llvm/llvm-project/commit/a615975bd9fe413f17ee43b231912ef2e8ccbd64
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tcgen05-smem-desc.mlir
Log Message:
-----------
[MLIR][NVVM] Add Op to create tcgen05-mma smem descriptor (#141651)
This patch adds an Op to create the shared-memory
descriptor for Tcgen05 MMA.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d1b0cbff806b50d399826e79b9a53e4726c21302
https://github.com/llvm/llvm-project/commit/d1b0cbff806b50d399826e79b9a53e4726c21302
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/test/CodeGenCXX/debug-info-class.cpp
M clang/test/CodeGenCXX/debug-info-template-member.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-diamond.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-multiple.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-simple-main.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-simple.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-virtual.cpp
M clang/test/Modules/ExtDebugInfo.cpp
Log Message:
-----------
[clang][DebugInfo] Add symbol for debugger with VTable information. (#130255)
The IR now includes a global variable for the debugger that holds
the address of the vtable.
Now every class that contains virtual functions, has a static
member (marked as artificial) that identifies where that vtable
is loaded in memory. The unmangled name is '_vtable$'.
This new symbol will allow a debugger to easily associate
classes with the physical location of their VTables using
only the DWARF information. Previously, this had to be done
by searching for ELF symbols with matching names; something
that was time-consuming and error-prone in certain edge cases.
Commit: 01848731d333eaf91101c40c695aaa1de183f7d1
https://github.com/llvm/llvm-project/commit/01848731d333eaf91101c40c695aaa1de183f7d1
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
M llvm/utils/update_givaluetracking_test_checks.py
Log Message:
-----------
[tools] Allow RegClass/Bank in update_givaluetracking_test_checks.py (#141727)
The script previously assumed an underscore after the :
Commit: b577438a879327dfb79b13bfc0122dd0434ebd92
https://github.com/llvm/llvm-project/commit/b577438a879327dfb79b13bfc0122dd0434ebd92
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
[SelectionDAG] Update documentation for VECTOR_[DE]INTERLEAVE nodes. NFC (#141644)
These can now support an arbitrary factor determined by the number of
operands/results. Fixes #141565
Commit: 63cb6af7825dc7b241853accfaca1de3018930be
https://github.com/llvm/llvm-project/commit/63cb6af7825dc7b241853accfaca1de3018930be
Author: Michele Scuttari <michele.scuttari at outlook.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Transforms.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
Log Message:
-----------
[MLIR] Add bufferization state to `getBufferType` and `resolveConflicts` interface methods (#141466)
The PR continues the work started in #141019 by adding the `BufferizationState` class also to the `getBufferType` and `resolveConflicts` interface methods, together with the additional support functions that are used throughout the bufferization infrastructure.
Commit: 783b39934623e734565c9d919b74d12c2f244f7d
https://github.com/llvm/llvm-project/commit/783b39934623e734565c9d919b74d12c2f244f7d
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M libcxx/docs/TestingLibcxx.rst
Log Message:
-----------
[libcxx][docs] Fix bullet point in Additional Tools section
Without a blank line after the ":", it was rendered on the same
line instead of a new one.
Commit: 2b9ded64b0221f4159ab603518c5f88edb8bf958
https://github.com/llvm/llvm-project/commit/2b9ded64b0221f4159ab603518c5f88edb8bf958
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/intrinsic-scalarize.ll
A llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
Log Message:
-----------
[VectorCombine] Support nary operands and intrinsics in scalarizeOpOrCmp (#138406)
This adds support for unary operands, and unary + ternary intrinsics in
scalarizeOpOrCmp (FKA scalarizeBinOpOrCmp).
The motivation behind this is to scalarize more intrinsics in
VectorCombine rather than in DAGCombine, so we can sink splats across
basic blocks: see https://github.com/llvm/llvm-project/pull/137786
The main change required is to generalize the existing VecC0/VecC1 rules
across n-ary ops:
- An operand can either be a constant vector or an insert of a scalar
into a constant vector
- If it's an insert, the index needs to be static and in bounds
- If it's an insert, all indices need to be the same across all operands
- If all the operands are constant vectors, bail as it will get constant
folded anyway
Commit: 5f39be591714eba1be413e2b3ed6fc152a15bb8e
https://github.com/llvm/llvm-project/commit/5f39be591714eba1be413e2b3ed6fc152a15bb8e
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/pr34438.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
M llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/constantfolder.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Use InstSimplifyFolder instead of TargetFolder (#141222)
For more powerful folding with operands that are not necessarily
all-constant, use InstSimplifyFolder instead of TargetFolder in
tryToConstantFold, and rename the function tryToFoldLiveIns.
Commit: 6296dd2b777107d1393753f8dd3aaee269157af6
https://github.com/llvm/llvm-project/commit/6296dd2b777107d1393753f8dd3aaee269157af6
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Log Message:
-----------
[LoopIdiom] Use m_scev_AffineAddRec with Loop matcher (NFC) (#141660)
Commit: f0f666bc3262f0ca6c7225116945e9feb67c14d0
https://github.com/llvm/llvm-project/commit/f0f666bc3262f0ca6c7225116945e9feb67c14d0
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
A llvm/test/Transforms/LoopUnroll/peel-last-iteration-debug.ll
A llvm/test/Transforms/LoopUnroll/peel-last-iteration-pointer-inductions.ll
Log Message:
-----------
[LoopPeel] Add peeling tests with debug value and pointer inductions
Adds extra test coverage for https://github.com/llvm/llvm-project/pull/140792.
Commit: 88f61f2c5c0ad9dad9c8df2fb86352629e7572c1
https://github.com/llvm/llvm-project/commit/88f61f2c5c0ad9dad9c8df2fb86352629e7572c1
Author: Will Froom <willfroom at google.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
Log Message:
-----------
[MLIR] Add missing forward declaration after 61d5fdf50c78 (#141734)
Commit: dc6aac5e3cda76c17295bebee6808b413c1051a2
https://github.com/llvm/llvm-project/commit/dc6aac5e3cda76c17295bebee6808b413c1051a2
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/source/Commands/CommandObjectThread.cpp
M lldb/source/Commands/Options.td
M lldb/test/API/functionalities/thread/jump/TestThreadJump.py
M lldb/test/API/functionalities/thread/jump/main.cpp
Log Message:
-----------
[Support] [lldb] Fix thread jump #45326 (#135778)
Fixes #45326
When you thread jump by calling
`j +2` or `thread jump --by +2` the offset is not recognised. This
commit fixes that.
---------
Signed-off-by: Ebuka Ezike <yerimyah1 at gmail.com>
Commit: 26bae798f27b17fe74a7c9c4f7abc489d44696d6
https://github.com/llvm/llvm-project/commit/26bae798f27b17fe74a7c9c4f7abc489d44696d6
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[SelectionDAG][AArch64] Add dot product lowering in NEON for PARTIAL_REDUCE_*MLA ISD nodes (#140075)
Lowering for fixed width vectors added to tablegen.
There is also custom lowering to ensure that the USDOT patterns are
still lowered for fixed width vectors. It also ensures that the
v16i8 -> v4i64 partial reduction case is lowered here instead of
being split (as there is not a v2i64 dot product instruction).
@JamesChesterman is the original author.
---------
Co-authored-by: James Chesterman <james.chesterman at arm.com>
Commit: 2e7489c8c82c4c0d1a28ae1725b0701b1af2413a
https://github.com/llvm/llvm-project/commit/2e7489c8c82c4c0d1a28ae1725b0701b1af2413a
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Fix build on gcc-7.5
Hopefully this fixes the build failure at
https://lab.llvm.org/buildbot/#/builders/116/builds/13423. gcc-14
seems to be able to deduce the type and compile this fine, but for
gcc-7 we need to avoid the Use/Value mismatch I guess.
Commit: 9262e37d8c2d77fd86a1b4c183ac3ab6fe076d30
https://github.com/llvm/llvm-project/commit/9262e37d8c2d77fd86a1b4c183ac3ab6fe076d30
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/fma.ll
M llvm/test/Transforms/InstCombine/fsh.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
Log Message:
-----------
[InstCombine] Fold shuffled intrinsic operands with constant operands (#141300)
We currently pull shuffles through binops and intrinsics, which is an
important canonical form for VectorCombine to be able to scalarize
vector sequences. But while binops can be folded with a constant
operand, intrinsics currently require all operands to be shufflevectors.
This extends intrinsic folding to be in line with regular binops by
reusing the constant "unshuffling" logic.
As far as I can tell the list of currently folded intrinsics don't
require any special UB handling.
This change in combination with #138095 and #137823 fixes the following
C:
```c
void max(int *x, int *y, int n) {
for (int i = 0; i < n; i++)
x[i] += *y > 42 ? *y : 42;
}
```
Not using the splatted vector form on RISC-V with `-O3 -march=rva23u64`:
```asm
vmv.s.x v8, a4
li a4, 42
vmax.vx v10, v8, a4
vrgather.vi v8, v10, 0
.LBB0_9: # %vector.body
# =>This Inner Loop Header: Depth=1
vl2re32.v v10, (a5)
vadd.vv v10, v10, v8
vs2r.v v10, (a5)
```
i.e., it now generates
```asm
li a6, 42
max a6, a4, a6
.LBB0_9: # %vector.body
# =>This Inner Loop Header: Depth=1
vl2re32.v v8, (a5)
vadd.vx v8, v8, a6
vs2r.v v8, (a5)
```
Commit: eea69691908d2ff59ef2614fc6f948d021d0ef07
https://github.com/llvm/llvm-project/commit/eea69691908d2ff59ef2614fc6f948d021d0ef07
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/promote-capture.ll
Log Message:
-----------
[LICM] Only check for provenance captures (#141731)
When performing scalar promotions, only consider provenance captures,
which may lead to non-thread-safe accesses. Address captures can be
ignored.
Commit: d1592a966bc22b94362380aa690eeb92f42b8ca0
https://github.com/llvm/llvm-project/commit/d1592a966bc22b94362380aa690eeb92f42b8ca0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/test/CodeGen/X86/avgceils.ll
M llvm/test/CodeGen/X86/avgfloors.ll
M llvm/test/CodeGen/X86/avx512-build-vector.ll
M llvm/test/CodeGen/X86/combine-or-shuffle.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/constant-pool-sharing.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/kmov.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pr30290.ll
M llvm/test/CodeGen/X86/pr46532.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/recip-fastmath.ll
M llvm/test/CodeGen/X86/recip-fastmath2.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/sqrt-fastmath.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/trunc-vector-width.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
Log Message:
-----------
[X86] X86FixupVectorConstantsPass - use scheduler model to avoid regressions (#140028)
When attempting to replace a full vector constant load with an instruction that uses a smaller constant, check the scheduler model to ensure the instruction isn't slower.
Throughput must not regress, but allow a small increase in latency based on how much constant data we're saving (I've used a simple estimate of 1 cycle per 128-bits of data saved).
NOTE: this currently ignores hoisted constant loads where the slower instruction might be acceptable.
Fixes #135998
Commit: 8b6e98559de15dc75edddf616ed37c5b6e23dfba
https://github.com/llvm/llvm-project/commit/8b6e98559de15dc75edddf616ed37c5b6e23dfba
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
Log Message:
-----------
[lldb][test] Skip DIL array subscript test on Windows
This has been flaky on Linaro's Windows on Arm bot, failing
with errors all along these lines:
Traceback (most recent call last):
File "C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\test\API\commands\frame\var-dil\basics\ArraySubscript\TestFrameVarDILArraySubscript.py", line 56, in test_subscript
self.expect_var_path("int_arr[100]", True, type="int")
File "C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\test\API\commands\frame\var-dil\basics\ArraySubscript\TestFrameVarDILArraySubscript.py", line 15, in expect_var_path
value_dil = super().expect_var_path(expr, value=value, type=type)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\packages\Python\lldbsuite\test\lldbtest.py", line 2589, in expect_var_path
value_check.check_value(self, eval_result, str(eval_result))
File "C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\packages\Python\lldbsuite\test\lldbtest.py", line 301, in check_value
test_base.assertSuccess(val.GetError())
File "C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\packages\Python\lldbsuite\test\lldbtest.py", line 2597, in assertSuccess
self.fail(self._formatMessage(msg, "'{}' is not success".format(error)))
AssertionError: 'read memory from 0x68119c00b0 failed (0 of 4 bytes read)' is not success
I think this is because we are trying to read off of the top of the
stack which is unmapped memory on Windows.
I have a fix I'm going to put in review shortly.
Commit: 63de20c0de05ce7b8b3968a9d210aa0f3d01acd4
https://github.com/llvm/llvm-project/commit/63de20c0de05ce7b8b3968a9d210aa0f3d01acd4
Author: Devon Loehr <DKLoehr at users.noreply.github.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/AST/DeclOpenMP.h
M clang/include/clang/Driver/Action.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Driver/ToolChains/Hexagon.h
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
Log Message:
-----------
Reland "Add macro to suppress -Wunnecessary-virtual-specifier" (#141091)
This fixes #139614 on non-clang compilers by moving `__has_warning`
completely inside the `#if defined(__clang__)` block. This prevents a
parse failure from compilers which don't recognize `__has_warning`.
Original description:
Followup to #138741.
This adds the requested macro to silence
`-Wunnecessary-virtual-specifier` when declaring virtual anchor
functions in `final` classes, per [LLVM
policy](https://llvm.org/docs/CodingStandards.html#provide-a-virtual-method-anchor-for-classes-in-headers).
It also cleans up any remaining instances of the warning, allowing us to
stop disabling it when we build LLVM.
Commit: c4d0d95a4fb92d65594f3575814a027815b5182f
https://github.com/llvm/llvm-project/commit/c4d0d95a4fb92d65594f3575814a027815b5182f
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
A clang/test/DebugInfo/KeyInstructions/multi-func.c
Log Message:
-----------
[KeyInstr][Clang] Reset atomGroup number for each function (#141607)
CGDebugInfo::completeFunction was added previously but mistakenly not
called (dropped through the cracks while putting together the patch
stack). Moved out of #134652 and #134654.
This patch is part of a stack that teaches Clang to generate Key Instructions
metadata for C and C++.
RFC:
https://discourse.llvm.org/t/rfc-improving-is-stmt-placement-for-better-interactive-debugging/82668
The feature is only functional in LLVM if LLVM is built with CMake flag
LLVM_EXPERIMENTAL_KEY_INSTRUCTIONs. Eventually that flag will be removed.
Commit: 0291f495dbea64231212a8d51ecef653e10aed33
https://github.com/llvm/llvm-project/commit/0291f495dbea64231212a8d51ecef653e10aed33
Author: zGoldthorpe <zgoldtho at ualberta.ca>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/test/Transforms/EarlyCSE/invariant-loads.ll
Log Message:
-----------
[EarlyCSE] Correcting assertion for DSE with invariant loads (#141495)
This patch corrects an assertion to handle an edge case where there is a
dead store into an `!invariant.load`'s pointer, but there is an
interleaving store to a different (non-aliasing) address.
In this case we know that the interleaved store cannot modify the
address even without MemorySSA, so the assert does not hold.
This bug was found through the AMD fuzzing project.
Commit: 5ab944a8c6a213beb96f3747a441b02e497732e4
https://github.com/llvm/llvm-project/commit/5ab944a8c6a213beb96f3747a441b02e497732e4
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/module.modulemap
A clang/lib/Headers/stdcountof.h
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/test/C/C2y/n3469.c
M clang/test/Modules/Inputs/builtin-headers/system-modules.modulemap
M clang/test/Modules/builtin-headers.mm
Log Message:
-----------
[C2y] Add stdcountof.h (#140890)
WG14 N3469 changed _Lengthof to _Countof but it also introduced the
<stdcountof.h> header to expose a macro with a non-ugly identifier. GCC
vends this header as part of the compiler implementation, so Clang
should do the same.
Suggested-by: Alejandro Colomar <alx at kernel.org>
Commit: 6d88343662c25e2b06974da9987d52f23a120b51
https://github.com/llvm/llvm-project/commit/6d88343662c25e2b06974da9987d52f23a120b51
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
Log Message:
-----------
[IA] Add support for [de]interleave{4,6,8} (#141512)
This teaches the interleaved access pass to the lower the intrinsics for
factors 4,6 and 8 added in #139893 to target intrinsics.
Because factors 4 and 8 could either have been recursively
[de]interleaved or have just been a single intrinsic, we need to check
that it's the former it before reshuffling around the values via
interleaveLeafValues.
After this patch, we can teach the loop vectorizer to emit a single
interleave intrinsic for factors 2 through to 8, and then we can remove
the recursive interleaving matching in interleaved access pass.
Commit: 34b6285735c999d2fab77b0ff8e5b497d86df3af
https://github.com/llvm/llvm-project/commit/34b6285735c999d2fab77b0ff8e5b497d86df3af
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
Log Message:
-----------
[AMDGPU] Treat image_msaa_load as a sampler operation (#141726)
While image_msaa_load does not take a sampler, it can behave as if it
does on some hardware. This has implications for wait counting and
clausing.
Commit: 6a477f6577a229589a610c36a879a1c88a4898a5
https://github.com/llvm/llvm-project/commit/6a477f6577a229589a610c36a879a1c88a4898a5
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/SMEInstrFormats.td
R llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
Log Message:
-----------
[AArch64] TableGen-erate SDNode descriptions (#140472)
This continues s-barannikov's work TableGen-erating SDNode descriptions.
This takes the initial patch from #119709 and moves documentation and the
rest of the AArch64ISD nodes to TableGen. Some issues were found by the
generated SDNode verification added in this patch. These issues have been
described and fixed in the following PRs:
- #140706
- #140711
- #140713
- #140715
---------
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
Commit: 6c86b7d7d8bc0f77242e938e68c0325acc7f04c3
https://github.com/llvm/llvm-project/commit/6c86b7d7d8bc0f77242e938e68c0325acc7f04c3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/fabs.ll
Log Message:
-----------
[ValueTracking][InstCombine] Generalize ignoreSignBitOfZero/NaN to handle more cases (#141015)
This patch was originally part of
https://github.com/llvm/llvm-project/pull/139861. It generalizes
`ignoreSignBitOfZero/NaN` to handle more instructions/intrinsics.
BTW, I find it mitigates performance regressions caused by
https://github.com/llvm/llvm-project/pull/141010 (IR diff
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2365/files). We don't
need to propagate FMF from fcmp into select, since we can infer demanded
properties from the user of select.
Commit: 3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7
https://github.com/llvm/llvm-project/commit/3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7
Author: David Green <david.green at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
A clang/include/clang/Basic/AArch64ACLETypes.def
R clang/include/clang/Basic/AArch64SVEACLETypes.def
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/module.modulemap
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/NSAPI.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Index/USRGeneration.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[AArch64] Rename AArch64SVEACLETypes.def and add base SVE_TYPE.
Commit: 5584020d8abf46f2852a59ed5333a7f2145bfec5
https://github.com/llvm/llvm-project/commit/5584020d8abf46f2852a59ed5333a7f2145bfec5
Author: Steven Perron <stevenperron at google.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGenHLSL/default_cbuffer.hlsl
Log Message:
-----------
[HLSL][SPIRV] Implement the SPIR-V target type for cbuffers. (#140061)
This change implement the type used to represent cbuffer for SPIR-V.
Fixes https://github.com/llvm/llvm-project/issues/138274.
Commit: f98bdd94e61721ebe11108956e63510692db34b2
https://github.com/llvm/llvm-project/commit/f98bdd94e61721ebe11108956e63510692db34b2
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopPeel.h
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-expansion-cost.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-constant-trip-count.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll
M llvm/test/Transforms/LoopUnroll/unroll-and-peel-last-iteration.ll
Log Message:
-----------
Reapply "[LoopPeel] Remove known trip count restriction when peeling last. (#140792)"
This reverts commit 580454526b936f7a576ddbc9bb932cf9be376ec4.
The recommitted version contains an extra check to not peel if the
latch exit is controlled by a pointer induction.
Original message:
Remove the restriction that the loop must be known to execute at least 2
iterations when peeling the last iteration. If we cannot prove at least
2 iterations are executed, a check and branch to skip the peeled loop is
inserted.
PR: https://github.com/llvm/llvm-project/pull/140792
Commit: 54ddbc6be3eeb91ae24f5e002fc1d0be7cb07654
https://github.com/llvm/llvm-project/commit/54ddbc6be3eeb91ae24f5e002fc1d0be7cb07654
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
Log Message:
-----------
[AMDGPU] fix amdgpu_max_num_work_groups in templates (#141633)
Clang does not instantiate amdgpu_max_num_work_groups attribute with one
template argument, causing
assertion codegen.
Fixes: https://github.com/llvm/llvm-project/issues/139570
Commit: 3d0f88552a43533799d9bf24cf4f61c89dd8af46
https://github.com/llvm/llvm-project/commit/3d0f88552a43533799d9bf24cf4f61c89dd8af46
Author: David Green <david.green at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[AArch64][LLDB] Add missing AArch64SVEACLETypes.def rename
Fixup from 3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7.
Commit: 618a399f862b68d3f4e3c2f39a1265dad8fd0e2f
https://github.com/llvm/llvm-project/commit/618a399f862b68d3f4e3c2f39a1265dad8fd0e2f
Author: Luke Lau <luke at igalia.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine] Explicitly match poison operand. NFCI (#141744)
This is a follow up from
https://github.com/llvm/llvm-project/pull/141300#discussion_r2109109224
Commit: ff5f8e513c6fb854cb11b05574c593c49f6f82d9
https://github.com/llvm/llvm-project/commit/ff5f8e513c6fb854cb11b05574c593c49f6f82d9
Author: Leonid Gorbunov <leon.tyumen at icloud.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
Log Message:
-----------
[MLIR][Presburger] removeTrivialRedundancy: skip unnecessary check for duplicate constraints (#138969)
`removeTrivialRedundancy` first marks duplicate rows redundant, then
when multiple rows differ only by a constant term, it removes all but
one of them. Since the latter removes all but one duplicate row as well,
it is unnecessary (redundant!) to mark duplicate rows redundant. So we
remove this step.
Commit: dcf3c79c36ac0e077eee26e8bc1e55d2eb99430c
https://github.com/llvm/llvm-project/commit/dcf3c79c36ac0e077eee26e8bc1e55d2eb99430c
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[NFC][AArch64] Add relnote saying modal FP8 intrinsics now fully implemented by ACLE (#141743)
Commit: 9aebf4c399598e4f4a61ea5115bbfdfacfaa6ce9
https://github.com/llvm/llvm-project/commit/9aebf4c399598e4f4a61ea5115bbfdfacfaa6ce9
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
Log Message:
-----------
[NFC][LLVM] Tests for vectorisation of loops with vscale base trip counts.
Commit: b8997c07d9783bbf81bf144b5982d43ba804f5ac
https://github.com/llvm/llvm-project/commit/b8997c07d9783bbf81bf144b5982d43ba804f5ac
Author: Charles Zablit <zablitcharles at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M lldb/docs/use/formatting.rst
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
A lldb/test/Shell/Settings/TestFrameFormatFunctionPrefix.test
Log Message:
-----------
[Demangling] Refactor Demangler range tracking (#140762)
This PR is a subset of the commits made in
https://github.com/swiftlang/llvm-project/pull/10710.
The most notable change is the addition of `PrefixRange` and
`SuffixRange` which are a catch-all to track anything after or before a
function's demangled name. In the case of Swift, this allows to add
support for name highlighting without having to track the range of the
scope and specifiers of a function (this will come in another PR).
Commit: 7fb2590c1d425bc2f1bb331de054418d9449dee4
https://github.com/llvm/llvm-project/commit/7fb2590c1d425bc2f1bb331de054418d9449dee4
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 6a477f6577a229589a610c36a879a1c88a4898a5
Commit: 11e804fcabce11a9fdfb4033263ef1e502cc8a72
https://github.com/llvm/llvm-project/commit/11e804fcabce11a9fdfb4033263ef1e502cc8a72
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang-tools-extra/clang-doc/tool/CMakeLists.txt
Log Message:
-----------
[clang-doc] Fix build break with BUILD_SHARED_LIBS=ON
The error message:
/usr/bin/ld: CMakeFiles/clang-doc.dir/ClangDocMain.cpp.o: undefined refe
rence to symbol '_Z20getMustacheHtmlFilesN4llvm9StringRefERN5clang3doc15
ClangDocContextE' /usr/bin/ld: /work/kparzysz/git/llvm.org/b/x86/./lib/l
ibclangDocSupport.so.21.0git: error adding symbols: DSO missing from com
mand line
collect2: error: ld returned 1 exit status
make[2]: *** [tools/clang/tools/extra/clang-doc/tool/CMakeFiles/clang-do
c.dir/build.make:107: bin/clang-doc] Error 1
Commit: b4bc8c6f83e3dc865cf6dccdc9f18edb6a2daa3f
https://github.com/llvm/llvm-project/commit/b4bc8c6f83e3dc865cf6dccdc9f18edb6a2daa3f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
M libc/test/integration/src/stdlib/CMakeLists.txt
A libc/test/integration/src/stdlib/gpu/CMakeLists.txt
A libc/test/integration/src/stdlib/gpu/malloc.cpp
A libc/test/integration/src/stdlib/gpu/malloc_stress.cpp
M libc/test/src/stdlib/malloc_test.cpp
Log Message:
-----------
[libc] Implement efficient 'malloc' on the GPU (#140156)
Summary:
This is the big patch that implements an efficient device-side `malloc`
on the GPU. This is the first pass and many improvements will be made
later.
The scheme revolves around using a global reference counted pointer to
hand out access to a dynamically created and destroyed slab interface.
The slab is simply a large bitfield with one bit for each slab. All
allocations are the same size in a slab, so different sized allocations
are done through different slabs.
Allocation is thus searching for or creating a slab for the desired
slab, reserving space, and then searching for a free bit. Freeing is
clearing the bit and then releasing the space.
This interface allows memory to dynamically grow and shrink. Future
patches will have different modes to allow fast first-time-use as well
as a non-RPC version.
Commit: 59b7b5b6b5c032ed21049d631eb5d67091f3a21c
https://github.com/llvm/llvm-project/commit/59b7b5b6b5c032ed21049d631eb5d67091f3a21c
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/OpenMP/declare-mapper.f90
M flang/test/Lower/OpenMP/map-mapper.f90
M flang/test/Parser/OpenMP/declare-mapper-unparse.f90
M flang/test/Parser/OpenMP/metadirective-dirspec.f90
M flang/test/Semantics/OpenMP/declare-mapper-symbols.f90
M flang/test/Semantics/OpenMP/declare-mapper03.f90
Log Message:
-----------
[OpenMP][Flang] Fix semantic check and scoping for declare mappers (#140560)
The current semantic check in place is incorrect, this patch fixes this.
Up to 1 **'default'** named mapper should be allowed for each derived
type.
The current semantic check only allows up to 1 **'default'** named
mapper across all derived types.
This also makes sure that declare mappers follow proper scoping rules
for both default and named mappers.
Co-authored-by: Raghu Maddhipatla <Raghu.Maddhipatla at amd.com>
Commit: 06ee672fc5222009d38fa8334b0b5438645f2a66
https://github.com/llvm/llvm-project/commit/06ee672fc5222009d38fa8334b0b5438645f2a66
Author: Omar Ahmed <omar.ahmed at codeplay.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/Ofast.c
M clang/test/Driver/cl-options.c
M clang/test/Driver/clang-translation.c
M clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[clang] Move opt level in clang toolchain to clang::ConstructJob start (#141036)
We currently transfer the opt level from the user clang call to CC1 args
at the end of the `ConstructJob` function, this might lead to bugs as
`ConstructJob` is a big function and we easily could add a change that
would return early from it. That would cause the opt level to not be
transferred to CC1 args and lead to wrong opt level compilation and
would be hard to spot. This PR moves the opt level to the beginning of
the function as opt level should be a direct transfer without any
problems, it also removes the redundancy where it was added 2 times
through the function.
Commit: 0ebe5557d9688f7397d45facb26efcd3f2c3bc8c
https://github.com/llvm/llvm-project/commit/0ebe5557d9688f7397d45facb26efcd3f2c3bc8c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M offload/liboffload/API/Device.td
M offload/liboffload/include/generated/OffloadAPI.h
M offload/liboffload/include/generated/OffloadPrint.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
Log Message:
-----------
[Offload] Add specifier for the host type (#141635)
Summary:
We use this sepcial type to indicate a host value, this will be refined
later but for now it's used as a stand-in device for transfers and
queues. It needs a special kind because it is not a device target as the
other ones so we need to differentiate it between a CPU and GPU type.
Fixes: https://github.com/llvm/llvm-project/issues/141436
Commit: 2b1ebef8b8a5af7092de80daafd2743683d0e8c8
https://github.com/llvm/llvm-project/commit/2b1ebef8b8a5af7092de80daafd2743683d0e8c8
Author: gbMattN <matthew.nagy at sony.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
Log Message:
-----------
Fixed small memory leak in libprofile (#141739)
Inside `getCurFilename`, there is this code snippit
```
if (!lprofCurFilename.FilenamePat || !lprofCurFilename.FilenamePat[0])
return 0;
```
If this is true, we return `"\0"`, but would leak the memory in
`FilenameBuf`.
This pull request adds a free before then to properly free the memory.
There was already a check that we allocated memory, so there is no need
to worry about freeing unallocated memory.
Commit: 5e28af04f32455f93975e227d08f502faa45247c
https://github.com/llvm/llvm-project/commit/5e28af04f32455f93975e227d08f502faa45247c
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/Sema/assume.c
Log Message:
-----------
[C] Fix parsing of [[clang::assume]] (#141747)
The assumption attribute is exposed with a Clang spelling, which means
we support __attribute__((assume)) as well as [[clang::assume]] as
spellings for the attribute.
In C++, the [[clang::assume]] spelling worked as expected. In C, that
spelling would emit an "unknown attribute ignored" diagnostic. This was
happening because we were failing to pass in the scope name and source
location when creating the attribute. In C++, this worked by chance
because [[assume]] is a known attribute in C++. But in C, where there is
thankfully no [[assume]] standard attribute, the lack of a scope meant
we would set the attribute kind to "unknown".
Commit: d58e00ddae0d4d6d68db565482aeb47597e00a25
https://github.com/llvm/llvm-project/commit/d58e00ddae0d4d6d68db565482aeb47597e00a25
Author: Udit Kumar Agarwal <udit.agarwal at intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
Log Message:
-----------
[CMake] Fix config when static zstd libraries are not found (#113584)
Fixes: https://github.com/llvm/llvm-project/issues/113583
Commit: 59a5c1f25f578bb1a4951a4610b4e683ee94a870
https://github.com/llvm/llvm-project/commit/59a5c1f25f578bb1a4951a4610b4e683ee94a870
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/no-exceptions.cpp
Log Message:
-----------
[clang][Sema] Diagnose exceptions only in non-dependent context in discarded `try/catch/throw` blocks (#139859)
Resolves #138939
When enabling `--fno-exceptions` flag, discarded statements containing
`try/catch/throw` in an independent context can be avoided from being
rejected.
Commit: 7fa365843d9f99e75c38a6107e8511b324950e74
https://github.com/llvm/llvm-project/commit/7fa365843d9f99e75c38a6107e8511b324950e74
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/mul-const-vector.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
A llvm/test/CodeGen/PowerPC/splat-extend.ll
M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
M llvm/test/CodeGen/PowerPC/vector-extend-sign.ll
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
Log Message:
-----------
[PowerPC] extend smaller splats into bigger splats (#141282)
For pwr9, xxspltib is a byte splat with a range -128 to 127 - it can be
used with a following vector extend sign to make splats of i16, i32, or
i64 element size. For pwr8, vspltisw with a following vector extend sign
can be used to make splats of i64 elements in the range -16 to 15.
Commit: 857ffa19156695a36798660326922a3537ab828a
https://github.com/llvm/llvm-project/commit/857ffa19156695a36798660326922a3537ab828a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Recursively start lifetimes as well (#141742)
The constructor starts the lifetime of all the subobjects.
Commit: 56594710c7ffdaf82e07b1ff63f01226c117b2ce
https://github.com/llvm/llvm-project/commit/56594710c7ffdaf82e07b1ff63f01226c117b2ce
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M libcxx/src/pstl/libdispatch.cpp
Log Message:
-----------
[libc++] Fix build failure with libdispatch backend (#141606)
We get an error "cannot add 'abi_tag' attribute in a redeclaration"
because functions like `__dispatch_apply` are first declared without an
ABI tag due to `_LIBCPP_BEGIN_EXPLICIT_ABI_ANNOTATIONS` inside the
header, and then redeclared with an ABI tag in the .cpp file.
Commit: 7f78ebf2484e6014ca845851483cfaf029746e5f
https://github.com/llvm/llvm-project/commit/7f78ebf2484e6014ca845851483cfaf029746e5f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M libcxx/src/pstl/libdispatch.cpp
Log Message:
-----------
Revert "[libc++] Fix build failure with libdispatch backend (#141606)"
It turns out that we're about to revert the patches that added these
annotations in the first place. I was too hasty to land this.
This reverts commit 56594710c7ffdaf82e07b1ff63f01226c117b2ce.
Commit: 1fe3de7ef49b7fb384e73e81fbe8fed35a999b2a
https://github.com/llvm/llvm-project/commit/1fe3de7ef49b7fb384e73e81fbe8fed35a999b2a
Author: Qinkun Bao <qinkun at google.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/tool/CMakeLists.txt
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
A clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/AST/DeclOpenMP.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/ASTMatchers/ASTMatchFinder.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
A clang/include/clang/Basic/AArch64ACLETypes.def
R clang/include/clang/Basic/AArch64SVEACLETypes.def
M clang/include/clang/Driver/Action.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/module.modulemap
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/NSAPI.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Hexagon.h
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/module.modulemap
A clang/lib/Headers/stdcountof.h
M clang/lib/Index/USRGeneration.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/C/C2y/n3469.c
M clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
M clang/test/CodeGenCXX/debug-info-class.cpp
M clang/test/CodeGenCXX/debug-info-template-member.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-diamond.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-multiple.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-simple-main.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-simple.cpp
A clang/test/CodeGenCXX/vtable-debug-info-inheritance-virtual.cpp
M clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/cbuffer.hlsl
M clang/test/CodeGenHLSL/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resource-bindings.hlsl
A clang/test/DebugInfo/KeyInstructions/multi-func.c
M clang/test/Driver/Ofast.c
M clang/test/Driver/cl-options.c
M clang/test/Driver/clang-translation.c
M clang/test/Driver/offload-Xarch.c
M clang/test/Modules/ExtDebugInfo.cpp
M clang/test/Modules/Inputs/builtin-headers/system-modules.modulemap
M clang/test/Modules/builtin-headers.mm
A clang/test/Sema/assume.c
M clang/test/SemaCXX/no-exceptions.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
M clang/tools/libclang/CIndex.cpp
M compiler-rt/lib/profile/InstrProfilingFile.c
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/OpenMP/declare-mapper.f90
M flang/test/Lower/OpenMP/map-mapper.f90
M flang/test/Parser/OpenMP/declare-mapper-unparse.f90
M flang/test/Parser/OpenMP/metadirective-dirspec.f90
M flang/test/Semantics/OpenMP/declare-mapper-symbols.f90
M flang/test/Semantics/OpenMP/declare-mapper03.f90
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
M libc/test/integration/src/stdlib/CMakeLists.txt
A libc/test/integration/src/stdlib/gpu/CMakeLists.txt
A libc/test/integration/src/stdlib/gpu/malloc.cpp
A libc/test/integration/src/stdlib/gpu/malloc_stress.cpp
M libc/test/src/stdlib/malloc_test.cpp
M libcxx/docs/TestingLibcxx.rst
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_nothrow.replace.indirect.pass.cpp
M lldb/docs/use/formatting.rst
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/source/Commands/CommandObjectThread.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/AddressRange.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py
M lldb/test/API/functionalities/thread/jump/TestThreadJump.py
M lldb/test/API/functionalities/thread/jump/main.cpp
A lldb/test/Shell/Settings/TestFrameFormatFunctionPrefix.test
M lldb/test/Shell/SymbolFile/Breakpad/stack-cfi-parsing.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-raSearch.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-stack-cfi.test
M lldb/test/Shell/SymbolFile/Breakpad/unwind-via-stack-win.test
M lldb/test/Shell/SymbolFile/target-symbols-add-unwind.test
M lldb/test/Shell/Unwind/basic-block-sections-with-dwarf-static.test
M llvm/cmake/config-ix.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/include/llvm/Transforms/Utils/LoopPeel.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/Object/OffloadBundle.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceImplicitBinding.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/CodeGen/AArch64/expand-select.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/tbz-tbnz.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vec_umulo.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
M llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll
M llvm/test/CodeGen/DirectX/BufferLoad.ll
M llvm/test/CodeGen/DirectX/BufferStore-errors.ll
M llvm/test/CodeGen/DirectX/BufferStore-sm61.ll
M llvm/test/CodeGen/DirectX/BufferStore.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/array-typedgep.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/arrays.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/scalars.ll
M llvm/test/CodeGen/DirectX/CBufferAccess/vectors.ll
M llvm/test/CodeGen/DirectX/CBufferLoadLegacy-errors.ll
M llvm/test/CodeGen/DirectX/CBufferLoadLegacy.ll
M llvm/test/CodeGen/DirectX/ContainerData/PSVResources-order.ll
M llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
M llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/arrays.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/multiple-spaces.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/simple.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/unbounded-arrays-error.ll
M llvm/test/CodeGen/DirectX/ImplicitBinding/unbounded-arrays.ll
M llvm/test/CodeGen/DirectX/Metadata/cbuffer-only.ll
M llvm/test/CodeGen/DirectX/Metadata/cbuffer_metadata.ll
M llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll
M llvm/test/CodeGen/DirectX/Metadata/srv_metadata.ll
M llvm/test/CodeGen/DirectX/Metadata/uav_metadata.ll
M llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll
M llvm/test/CodeGen/DirectX/RawBufferLoad.ll
M llvm/test/CodeGen/DirectX/RawBufferStore-error64.ll
M llvm/test/CodeGen/DirectX/RawBufferStore.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/load_rawbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/store_rawbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll
M llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.5.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs-array-valver1.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/max-64-uavs.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/raw-and-structured-buffers.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-alias-0.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-alias-1.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.6.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-sm6.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/res-may-not-alias-valver1.8.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.7.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-lib-valver1.8.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/uavs-at-every-stage-vs.ll
M llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
M llvm/test/CodeGen/DirectX/resource_counter_error.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/mul-const-vector.ll
M llvm/test/CodeGen/PowerPC/p10-fi-elim.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
A llvm/test/CodeGen/PowerPC/splat-extend.ll
M llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
M llvm/test/CodeGen/PowerPC/vector-extend-sign.ll
M llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/zilsd.ll
M llvm/test/CodeGen/X86/avgceils.ll
M llvm/test/CodeGen/X86/avgfloors.ll
M llvm/test/CodeGen/X86/avx512-build-vector.ll
M llvm/test/CodeGen/X86/combine-or-shuffle.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/constant-pool-sharing.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/kmov.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pr30290.ll
M llvm/test/CodeGen/X86/pr46532.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/recip-fastmath.ll
M llvm/test/CodeGen/X86/recip-fastmath2.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/sqrt-fastmath.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/trunc-vector-width.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/MC/RISCV/xqcilb-valid.s
M llvm/test/MC/RISCV/xqcili-valid.s
M llvm/test/Transforms/EarlyCSE/invariant-loads.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/fma.ll
M llvm/test/Transforms/InstCombine/fsh.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LICM/promote-capture.ll
A llvm/test/Transforms/LoopUnroll/peel-last-iteration-debug.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-expansion-cost.ll
A llvm/test/Transforms/LoopUnroll/peel-last-iteration-pointer-inductions.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-constant-trip-count.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-variable-trip-count.ll
M llvm/test/Transforms/LoopUnroll/unroll-and-peel-last-iteration.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-loop-backedge-elimination-epilogue.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/pr34438.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
M llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
M llvm/test/Transforms/LoopVectorize/constantfolder.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/VectorCombine/intrinsic-scalarize.ll
A llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
R llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/DirectX/ResourceBindingAnalysisTests.cpp
M llvm/unittests/Target/DirectX/UniqueResourceFromUseTests.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/update_givaluetracking_test_checks.py
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Transforms.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/Transforms/BufferizableOpInterfaceImpl.cpp
A mlir/test/Target/LLVMIR/nvvm/tcgen05-smem-desc.mlir
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
M offload/liboffload/API/Device.td
M offload/liboffload/include/generated/OffloadAPI.h
M offload/liboffload/include/generated/OffloadPrint.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/qinkunbao/spr/ubsan-support-srcsanitize-for-multiple-ignorelists
Compare: https://github.com/llvm/llvm-project/compare/12b023f4e31a...1fe3de7ef49b
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