[all-commits] [llvm/llvm-project] d1592a: [X86] X86FixupVectorConstantsPass - use scheduler ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1592a966bc22b94362380aa690eeb92f42b8ca0
      https://github.com/llvm/llvm-project/commit/d1592a966bc22b94362380aa690eeb92f42b8ca0
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-05-28 (Wed, 28 May 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
    M llvm/test/CodeGen/X86/avgceils.ll
    M llvm/test/CodeGen/X86/avgfloors.ll
    M llvm/test/CodeGen/X86/avx512-build-vector.ll
    M llvm/test/CodeGen/X86/combine-or-shuffle.ll
    M llvm/test/CodeGen/X86/combine-or.ll
    M llvm/test/CodeGen/X86/constant-pool-sharing.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
    M llvm/test/CodeGen/X86/kmov.ll
    M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
    M llvm/test/CodeGen/X86/min-legal-vector-width.ll
    M llvm/test/CodeGen/X86/pr30290.ll
    M llvm/test/CodeGen/X86/pr46532.ll
    M llvm/test/CodeGen/X86/pr57340.ll
    M llvm/test/CodeGen/X86/pr63108.ll
    M llvm/test/CodeGen/X86/pr77459.ll
    M llvm/test/CodeGen/X86/recip-fastmath.ll
    M llvm/test/CodeGen/X86/recip-fastmath2.ll
    M llvm/test/CodeGen/X86/slow-pmulld.ll
    M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
    M llvm/test/CodeGen/X86/sqrt-fastmath.ll
    M llvm/test/CodeGen/X86/sse-domains.ll
    M llvm/test/CodeGen/X86/trunc-vector-width.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll

  Log Message:
  -----------
  [X86] X86FixupVectorConstantsPass - use scheduler model to avoid regressions (#140028)

When attempting to replace a full vector constant load with an instruction that uses a smaller constant, check the scheduler model to ensure the instruction isn't slower.

Throughput must not regress, but allow a small increase in latency based on how much constant data we're saving (I've used a simple estimate of 1 cycle per 128-bits of data saved).

NOTE: this currently ignores hoisted constant loads where the slower instruction might be acceptable.

Fixes #135998



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