[all-commits] [llvm/llvm-project] 26bae7: [SelectionDAG][AArch64] Add dot product lowering i...

[Nicholas Guy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 26bae798f27b17fe74a7c9c4f7abc489d44696d6
      https://github.com/llvm/llvm-project/commit/26bae798f27b17fe74a7c9c4f7abc489d44696d6
  Author: Nicholas Guy <nicholas.guy at arm.com>
  Date:   2025-05-28 (Wed, 28 May 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll

  Log Message:
  -----------
  [SelectionDAG][AArch64] Add dot product lowering in NEON for PARTIAL_REDUCE_*MLA ISD nodes (#140075)

Lowering for fixed width vectors added to tablegen.
There is also custom lowering to ensure that the USDOT patterns are
still lowered for fixed width vectors. It also ensures that the
v16i8 -> v4i64 partial reduction case is lowered here instead of
being split (as there is not a v2i64 dot product instruction).

@JamesChesterman is the original author.

---------

Co-authored-by: James Chesterman <james.chesterman at arm.com>



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