[all-commits] [llvm/llvm-project] 6c917f: [AMDGPU][SDAG] Initial support for ISD::PTRADD

[Fabian Ritter via All-commits]

  Branch: refs/heads/users/ritter-x2a/05-27-_amdgpu_sdag_initial_support_for_isd_ptradd
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c917f223ab80ff4a28ddc7b93eec2ec96316929
      https://github.com/llvm/llvm-project/commit/6c917f223ab80ff4a28ddc7b93eec2ec96316929
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2025-05-28 (Wed, 28 May 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
    M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
    M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    A llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll

  Log Message:
  -----------
  [AMDGPU][SDAG] Initial support for ISD::PTRADD

Enable generation of PTRADD SelectionDAG nodes for pointer arithmetic for SI,
for now behind an internal CLI option. Also add basic patterns to match these
nodes. Optimizations will come in follow-up PRs. Basic tests for SDAG codegen
with PTRADD are in test/CodeGen/AMDGPU/ptradd-sdag.ll

Since GlobalISel also uses the PTRADD SDAG patterns via SelectionDAGCompat,
this change affects GlobalISel tests:
- Uniform 32-bit address arithmetic is now lowered to s_add_i32 instead of
  s_add_u32, which is consistent to what SDAG does (and gives
  SIShrinkInstructions the chance to generate s_addk_i32).
- 64-bit address arithmetic uses the [sv]_add_u64 pseudos, which is consistent
  with SDAG and means that GISel now generates 64-bit adds for gfx12. The only
  drawback with that is that we could save 1-2 instructions if we didn't use
  64-bit adds with >32-bit immediate (two movs with 32-bit immediates,
  s_delay_alu, and a 64-bit add vs two 32-bit adds with immediate), but that's
  a separate problem.
- The register class for the dead carry-out/sign-bit operand of
  V_ADD_CO_U32_e64 on architectures without carry-less additions now is sreg_64
  instead of sreg_64_xexec. I'm not sure if that loses us something worth
  preserving; I haven't found an obvious way to avoid this.

Overall, the changes in the GlobalISel tests seem to be improvements.



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