[all-commits] [llvm/llvm-project] 94f8e4: RISCV: Remove faulty assert that ignored subregist...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/riscv/remove-subreg-ignoring-assert
  Home:   https://github.com/llvm/llvm-project
  Commit: 94f8e48435f37a0d0b21dd483a6664efd4eaf68a
      https://github.com/llvm/llvm-project/commit/94f8e48435f37a0d0b21dd483a6664efd4eaf68a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-05-27 (Tue, 27 May 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
    A llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir

  Log Message:
  -----------
  RISCV: Remove faulty assert that ignored subregister uses

This was asserting the raw virtual register class was a scalar
class, instead of computing the net result of the register class
plus the subregister index on the operand. The machine verifier
should be checking this was a valid combination in the first place,
so just drop the assert.



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